Understanding the Cascode Amplifier Configuration and Its Practical Schematic

cascode amplifier circuit diagram

For demanding applications requiring minimal distortion and high gain, stack a common-emitter stage directly above a common-base stage. This arrangement isolates the input from output capacitance while maintaining a near-constant collector voltage on the lower transistor, eliminating Miller-effect degradation. Bias the lower device with a 5–10 V drop across its collector-emitter junction to ensure linear operation; exceed 15 V and risk breakdown that compromises performance.

Use a current source in the emitter leg of the upper transistor–typically a resistor sized for 1–2 mA quiescent current–to decouple AC signals without destabilizing DC bias. Capacitors at input and output should be chosen for corner frequencies at least a decade below the lowest operating frequency; 100 nF for audio, 1 pF for RF, ensuring they don’t add reactive loading that shifts phase or reduces bandwidth.

Place a 1–10 kΩ resistor between the base of the upper device and a reference node–ground or a low-impedance supply–if driving inductive loads. This prevents oscillation by damping the resonance formed with parasitic capacitances. Measure output impedance with a network analyzer: expect 10–100 Ω in typical configurations, rising only 20% when swapping BJTs for MOSFETs with lower transconductance.

Ground the lower stage’s base through a bypass capacitor sized to short noise–minimum 100 nF ceramic–to prevent feedback loops corrupting low-level signals. If using discrete components, match β within 10% between paired transistors; mismatched gain introduces even-order harmonics visible on a spectrum analyzer above 0 dBc. Layout traces with minimal loop area; inductance above 10 nH per cm noticeably rolls off response above 50 MHz.

Thermal drift offsets DC operating points by 2 mV/°C for silicon; stabilize using thermal pads or a matched constant-current sink on the lower device. Verify stability with step-response tests: overshoot exceeding 5% indicates phase margin below 45°, requiring compensation via reduced collector resistor or increased emitter degeneration.

High-Gain Two-Stage Transconductance Layout Guide

Select a common-emitter first stage with a low output impedance transistor, such as a 2N3904, biased at 500 µA collector current for optimal transconductance. Place a resistor of 2 kΩ between the base and ground to stabilize operating point against thermal drift, ensuring the base voltage remains at 0.7 V.

Position the second device–a common-base configuration–directly atop the emitter of the lower transistor, using a high breakdown voltage variant like the MPSA42 for input swings exceeding ±10 V. Connect its base to a fixed reference 3.3 V via a 10 kΩ resistor; this isolates the input capacitance of the upper stage, reducing Miller effect by over 90%.

Insert a bypass capacitor of 100 nF between the upper base node and ground, cutting high-frequency noise by 20 dB above 1 MHz. Keep lead lengths under 5 mm to prevent parasitic inductance from degrading bandwidth.

Use a current mirror on the upper collector to set quiescent current at 600 µA, matching the lower stage’s output impedance for symmetric push-pull operation. Load the upper stage with a 1.5 kΩ resistor for a voltage gain of 120 V/V–verified with SPICE at 1 kHz.

Ground the emitter of the lower device through a 1 kΩ resistor shunted by 1 µF film capacitor, establishing a dominant pole at 160 Hz for AC stability. Avoid electrolytic capacitors here; their equivalent series resistance introduces phase shift above 10 kHz.

Route the signal path with 50 Ω microstrip traces on the PCB, maintaining consistent impedance from the input coupling capacitor to the load. Keep the feedback network–if used–separate from the high-impedance nodes to prevent unwanted coupling.

Test the configuration with a 10 mVpp sinusoidal input at 1 kHz; expect a THD below 0.05% if layout parasitics are minimized. Replace the upper transistor if input capacitance exceeds 3 pF–measured with an LCR meter–otherwise, upper-frequency cutoff drops below 5 MHz.

Key Components Required for a High-Gain Voltage Stage Assembly

Select active devices with high output impedance and low feedback capacitance. Bipolar junction transistors (BJTs) like the 2N3904 or field-effect transistors (FETs) such as the 2N5457 are optimal for their ability to minimize Miller effect distortion. Ensure the chosen parts have a transition frequency (fT) at least ten times higher than the intended operating bandwidth to prevent phase shifts.

Base bias resistors must precisely set quiescent current without thermal runaway risks. Use low-tolerance (1% or better) metal film resistors in the 10kΩ to 1MΩ range, paired with temperature-stable voltage references. For emitter/source degeneration, opt for 10Ω to 1kΩ values with a power rating of at least 0.25W to handle transient currents.

Coupling capacitors should exhibit low equivalent series resistance (ESR) and high dielectric stability. Film capacitors (polypropylene or polystyrene) in the 10nF to 10µF range suit signal paths, while electrolytics are acceptable only for power supply decoupling where ESR is less critical. Avoid ceramic capacitors for large-signal applications due to voltage coefficient nonlinearities.

Load and tail current sources demand high output impedance to maintain linearity. Discrete current mirrors using matched BJTs (e.g., MAT03) or FET-based sinks (e.g., DN2540) provide superior performance over resistor-based alternatives. For precision, incorporate laser-trimmed monolithic current sources like the LM334, ensuring compliance voltage margins exceed 2V.

Stability compensation networks typically require a dominant pole approach. Place a small capacitor (10pF to 100pF) between the high-impedance node and ground to roll off high-frequency gain. Verify phase margin via transient analysis or Bode plots, targeting at least 60° at unity gain frequency. Avoid overcompensation, as it degrades settling time.

Power supply filtering must eliminate ripple while preserving bandwidth. Use low-dropout regulators (LDOs) like the LT3045 for analog rails, followed by π-section RC filters with cutoff frequencies below 10Hz. Bulk decoupling capacitors (100µF to 1000µF tantalum) should be placed within 2cm of the active devices to suppress high-frequency noise.

Layout considerations prioritize minimizing parasitic inductance and capacitance. Route signal traces as short, direct paths with ground planes beneath high-impedance nodes. Separate analog and digital grounds, connecting them at a single point near the power supply. Use star grounding for sensitive stages and avoid shared return paths for input/output currents.

Building Multi-Transistor Stage Arrangements: A Practical Guide

Select transistors with matching gain characteristics to minimize distortion. For low-noise stages, use devices with noise figures below 2 dB at your target frequency. Begin with a pair of NPN or PNP types rated for similar current capacities–typically 2N3904/2N3906 or BC547/BC557. Avoid mixing different semiconductor technologies (e.g., silicon-germanium with standard silicon) unless compensating for temperature effects.

Place the lower device first, biasing it in the active region. Calculate base resistor values using Rb = (Vcc - Vbe) / Ib, where Ib should be 1–5% of the collector current. For a 5 mA collector current, aim for 50–250 µA base current. Use a trimmer potentiometer for fine adjustments during testing.

  • Collector-emitter voltage for the lower stage: 3–6V maximum
  • Base-emitter junction temperature: keep below 125°C
  • Collector current stability: ±1% variation under load

Solder the upper device directly above the first, ensuring thermal coupling via a shared heatsink if power exceeds 250 mW. Connect the emitter of the upper transistor to the collector of the lower one–this stacked configuration doubles the breakdown voltage while maintaining high input impedance. For RF applications, keep lead lengths under 5 mm to reduce parasitic inductance.

Apply a constant current source to the stacked pair’s combined collector. A simple two-resistor divider (R1/R2 ratio of 1:10) with a bypass capacitor (10 µF tantalum) stabilizes operating points. For higher precision, substitute with an active load (e.g., a current mirror using matched diodes).

  1. Measure DC voltages at each node before input signal application
  2. Verify Vce across upper device: should be 50–70% of supply voltage
  3. Check quiescent current: target 1–10 mA depending on gain needs

Couple the input signal through a 1 µF coupling capacitor to block DC offset. Use a 10 kΩ resistor between the base of the lower device and ground to set input impedance. For impedance matching, add a series resistor (50–300 Ω) at the input if driving from low-impedance sources like microphones or mixers.

Terminate the output with a 10–100 µF capacitor to isolate DC from subsequent stages. Load the output with a resistor (1–10 kΩ) to prevent voltage swings beyond the linear region. Test with a 1 kHz sine wave at 10 mVpp–harmonic distortion should remain under 0.5%. Adjust upper transistor’s bias until both stages switch symmetrically around the signal zero-crossing.

Encapsulate the arrangement in a grounded metal enclosure if operating above 10 MHz. Use ferrite beads on power leads to suppress high-frequency noise. For variable-gain designs, insert a 1 kΩ potentiometer between the emitters of both transistors–this modulates transconductance without affecting DC operating points.