Complete Guide to Building a Practical Metal Detector Circuit

For precision applications requiring accurate frequency mixing analysis, a double-balanced mixer paired with a Schottky diode array outperforms conventional designs. The schematic should include a local oscillator (LO) running at 10 MHz with a +7 dBm output, feeding into Mini-Circuits ADE-1LH mixers via a Wilkinson power divider. This configuration suppresses unwanted harmonics by at least 35 dB, ensuring cleaner intermediate frequency (IF) extraction.

Critical component selection: Use surface-mount capacitors with NP0 dielectric for C3-C6 (100 pF each) to maintain stability across temperature ranges (−40°C to +85°C). The IF amplifier stage demands a low-noise op-amp like the OPA2171, configured for a gain of 20 dB with a 10 kΩ feedback resistor. Bypass capacitors (0.1 µF) must be placed within 2 mm of each IC’s power pin to prevent high-frequency oscillations, a common failure point in prototype testing.

Grounding strategy separates analog and digital sections using a star topology. Connect the analog ground plane directly to the power supply’s ground via a 1 mm trace, avoiding daisy-chaining. For the output filter, a third-order Chebyshev low-pass network (cutoff at 5 MHz) minimizes signal distortion. Resistor values (R1=51 Ω, R2=200 Ω) balance impedance matching while preventing reflections exceeding −15 dB return loss.

Avoid these pitfalls: Skipping the LO buffer stage reduces conversion efficiency by 18%, while improper shielding increases noise pickup by 12 dB at 1 GHz. Test the IF output with a spectrum analyzer set to 10 kHz RBW; harmonics should remain below −50 dBm. If phase noise exceeds −110 dBc/Hz at 10 kHz offset, replace the LO source with a low-phase-noise oscillator like the Crystek CVCO55CC.

Building a High-Performance Signal Mixer Layout

Start with a balanced diode ring modulator as the core of your mixer stage–this configuration minimizes distortion and improves sideband suppression. Use Schottky diodes like the 1N5711 for low-noise operation and fast switching. Arrange them in a quad bridge with precise symmetry; even minor mismatches degrade performance. Include a trimmer capacitor (5–20 pF) across one diode pair to fine-tune carrier leakage levels below -50 dB.

Choose a low-noise op-amp for the intermediate frequency (IF) amplifier stage. The OPA2134 provides 8 MHz bandwidth and 8 nV/√Hz noise density, ideal for 455 kHz IF systems. Power the op-amp with ±12V rails to handle large signals without clipping. Add a 100 Ω input resistor to isolate the mixer from the op-amp’s input capacitance, preventing oscillations. Use a 1:1 bifilar-wound transformer at the input to maintain impedance balance and reject common-mode noise.

For the local oscillator (LO), use a Colpitts configuration with a JFET like the J310. This topology offers stable frequency control and low phase noise. Set the tank circuit components to resonate at your desired LO frequency–e.g., 10 MHz for an IF of 455 kHz with a 10.455 MHz signal. Include a varactor diode (MV209) for fine frequency adjustment (±50 kHz). Power the JFET with 9V and decouple the supply with a 100 nF capacitor to ground, placed within 5 mm of the device.

Component	Recommended Value	Purpose
Schottky diodes	1N5711 (×4)	Balanced mixer core
Op-amp	OPA2134	IF amplification
JFET	J310	Local oscillator
Varactor diode	MV209	Frequency tuning
Input transformer	Bifilar-wound 1:1	Impedance matching

Ground all critical paths to a single star point to avoid ground loops. Connect the mixer output, op-amp return, and oscillator ground to this point using 0.5 mm-wide traces on a double-sided PCB. Use a ground plane on the bottom layer to reduce inductance. Keep signal traces short–under 25 mm–to minimize parasitic capacitance and crosstalk. Route the LO path away from the IF and RF lines; maintain at least 5 mm separation to prevent unintended coupling.

Add a low-pass filter at the mixer output to reject the unwanted sideband. For a 455 kHz IF, use a 4-pole Chebyshev filter with a 3 dB cutoff at 500 kHz. Components should be 1% tolerance (e.g., 100 nH inductors, 330 pF capacitors) to maintain filter shape. Include a 50 Ω output buffer (e.g., LT1220) to drive subsequent stages without loading the filter. Test the filter response with a network analyzer; adjust component values if the passband ripple exceeds 0.5 dB.

Use shielded enclosures for the LO and mixer sections to block external interference. Place the LO in a separate cavity if operating above 30 MHz. Connect shields to the star ground with multiple vias. For DIY builds, a machined aluminum box with subdividers works better than a tinned steel enclosure. Drill ventilation holes if thermal dissipation is a concern–e.g., for power amplifiers–but omit them near sensitive circuits to prevent RF ingress.

Calibrate the system with a signal generator and spectrum analyzer. Set the LO level to 7–10 dBm for optimal mixer efficiency without excessive harmonics. Measure the IF output at 455 kHz; expect -10 dBm for a -20 dBm RF input. Check for spurs–significant components should be >50 dB below the carrier. If LO feedthrough is visible, adjust the trimmer capacitor in 1 pF increments until it disappears. Document the final settings for repeatability.

For digital interfacing, tap the IF stage output before the filter. Use a high-speed ADC like the AD9226 (25 MSPS) to sample the signal. Route the analog path with controlled impedance (50 Ω) to the ADC. Add a series ferrite bead (600 Ω at 100 MHz) at the ADC input to block high-frequency noise. Keep the digital ground separate from the analog ground, connecting them only at the ADC’s ground pin to prevent digital noise from degrading sensitivity.

Core Elements for Constructing a Heterodyne Mixer Assembly

Select a dual-gate MOSFET like the BF998 or 3SK122 as the nonlinear mixing element–these offer superior isolation between input ports and lower noise compared to diode rings. Ensure the device operates within its specified gate-source cutoff voltage (typically 2–4V) to maintain optimal conversion gain while minimizing intermodulation distortion. Include a decoupling network on the drain supply (100nF ceramic + 10μF tantalum) to suppress local oscillator leakage into the IF output.

For the local oscillator stage, prioritize a Colpitts configuration using a 2N3904 or 2SC1970 transistor, stabilized with a 10MHz crystal or varactor-tuned LC tank. The tank’s Q-factor should exceed 100 to reduce phase noise, achieved with air-core inductors (0.5–2μH) and precision capacitors (1–33pF NP0). Buffer the oscillator output with a unity-gain emitter follower to prevent load pulling, isolating it from the mixer’s input impedance (~1kΩ).

Match the intermediate frequency (IF) port impedance (50–200Ω) using a Pi-network or transformer (FT37-43 core with bifilar windings) to maximize signal transfer. Add a 3-pole Chebyshev filter at the IF output–center frequency ±5kHz, 0.5dB ripple–to reject image frequencies and spurious emissions. Use 1N4148 diodes in clamping circuits to protect the mixer from transients exceeding ±0.7V, especially in high-dynamic-range applications.

Step-by-Step Wiring Guide for a Single-Balanced Diode Ring Converter

Begin by selecting four fast-switching Schottky diodes (e.g., 1N5711 or HSMS-2850) with matched forward voltage drops (±10 mV) and reverse recovery times under 10 ns. Mount them in a ring configuration on a prototyping board with a ground plane or a double-sided PCB to minimize parasitic inductance. Ensure the RF input and local oscillator (LO) ports are isolated by at least 40 dB–use separate striplines on opposite sides of the board or shielded coaxial cables if wiring by hand. The IF output should connect via a balun or center-tapped transformer to reject common-mode noise; a Mini-Circuits T1-1T-KK81 or equivalent wound on a FT37-43 ferrite core works for 1–50 MHz applications.

• LO Port: Apply +7 dBm at twice the desired IF frequency (e.g., 28 MHz for a 14 MHz output) to the ring’s mid-point via a 1:1 balun. Verify signal purity with a spectrum analyzer; harmonics should stay below -40 dBc. Add a low-pass π-network (two 33 pF capacitors to ground, one 1.2 μH inductor in series) to suppress LO feedthrough.
• RF Port: Attenuate the incoming signal to -20 dBm before feeding it into the opposing mid-point of the diode ring. Use a 6 dB pad if the source exceeds -10 dBm to avoid diode saturation and intermodulation distortion above -70 dBm/MHz. Keep lead lengths under 5 mm–solder diodes directly to the board or use SMA connectors with minimal coax stubs.
• IF Port: Terminate the output with a diplexer: a 1.5 kΩ resistor in parallel with a 330 pF capacitor for high-pass filtering (removes LO leakage) and a 2.2 μH inductor in series with a 100 Ω load for low-pass (extracts the desired beat frequency). Measure conversion loss with a vector network analyzer; target 6–8 dB for 1–30 MHz operation.

Test the assembly in stages. First, inject a 0 dBm, 10 MHz LO and confirm diode conduction with an oscilloscope–you should see clean, symmetrical switching at the IF port without clipping. Introduce a -30 dBm RF signal at 10.001 MHz; the output must show a stable 1 kHz tone with no spurious responses above -60 dBc. Adjust the LO power in 1 dB steps–optimal conversion loss occurs at +6 to +9 dBm, beyond which diode impedance mismatch degrades performance. For final validation, plot two-tone intermodulation ratios (IMD3) with inputs at -20 dBm and -21 dBm spaced 2 kHz apart; IMD3 should remain below -45 dBc.