How to Build a UC3845B PWM Controller Circuit Schematic Guide
Start with a 12V input feeding a current-mode PWM IC through a 150Ω resistor to the VCC pin, bypassed by a 100nF capacitor grounded nearby. This pairing stabilizes startup transients and prevents latch-up during input surges. Add a 1kΩ feedback resistor from the output rail to the COMP pin, shunted by a 47pF capacitor to GND–this defines the dominant pole, keeping crossover at 50kHz with
For gate drive, connect a totem-pole output stage using a 2N2222 pull-up (10Ω resistor to 12V) and an IRF540N for the low-side switch. The 5V reference should be decoupled with a 1µF tantalum capacitor within 2mm of the REF pin and fed to an adjustable resistor divider (10kΩ/20kΩ) to set the error amplifier threshold. Avoid routing the feedback trace parallel to the switching node–use a guard ring tied to the IC’s analog ground to cut noise by 18dB.
On the sensing side, terminate the current-sense resistor (RS) directly at the source of the MOSFET, not at the IC pin. A 0.1Ω RS with a 1ns rise-time clamp diode (BAT54) prevents false triggers under 6A peak loads. For slope compensation, tie a 10kΩ resistor from the oscillator timing capacitor (CT) to the current-sense pin–this linearizes the control loop above 50% duty cycle without requiring additional op-amps.
Layout priority: place the GND vias for the IC, CT timing capacitor, and RS within a 5mm radius. Use a 50mm² copper pour for the switching node to limit temperature rise to 10°C/W. Test the loop stability by injecting a 10mV sine wave at COMP–adjust the 47pF compensation cap in 5pF steps until the gain margin flattens at -12dB at 100kHz.
Practical Implementation of the Current-Mode PWM Controller
Begin by configuring the compensation network with precision–place a 2.2nF capacitor in parallel with a 22kΩ resistor between the error amplifier output (pin 1) and its inverting input (pin 2) for stable feedback loop dynamics. Ensure the oscillator timing components (RT and CT) adhere to values of 10kΩ and 1nF respectively to achieve a reliable 100kHz switching frequency; deviations beyond ±10% compromise transient response and audible noise suppression. For input decoupling, use a 47μF low-ESR capacitor (X5R or X7R dielectric) within 2mm of the VCC pin (pin 7) and an additional 0.1μF ceramic capacitor for high-frequency noise filtering–omitting this step risks erratic behavior under load transients.
Critical Component Selection Table
| Function | Component | Recommended Value | Note |
|---|---|---|---|
| Current sense resistor | Shunt resistor | 0.1Ω–0.5Ω | 5W power rating; Kelvin connection mandatory |
| Gate driver pull-up | Resistor | 10Ω–47Ω | 1W rating; adjust for MOSFET rise/fall times |
| Soft-start capacitor | Film or ceramic | 0.1μF–1μF | X7R dielectric; avoid electrolytic |
| Snubber network | RC pair | 10Ω + 1nF | Placed across MOSFET drain-source; dampens ringing |
Isolate the current sense path with a 100Ω series resistor and a 1nF capacitor to ground at the sensing pin (pin 3) to minimize noise coupling–this prevents false triggering during switching transitions. For the power MOSFET, select a device with a gate charge (Qg) under 50nC and a breakdown voltage exceeding 1.5× the input rail; IRFB4110 or IPP075N10N3 are proven choices. Terminate the shutdown pin (pin 4) with a 10kΩ pull-down resistor if unused; leaving it floating invites erratic startup sequences.
Key Pin Configuration and Their Practical Functions
Start by wiring the feedback input (pin 2) through a precision voltage divider to the output voltage node–this ensures stable regulation. Use a 1% tolerance resistor network with a ratio of 1:2 (e.g., 10kΩ and 20kΩ) to scale the output to the internal 2.5V reference. Bypass this pin with a 0.1µF ceramic capacitor directly to ground to filter high-frequency noise, preventing false triggering of the error amplifier.
Compensation and Current Sensing
Connect the compensation pin (pin 1) via a 22kΩ resistor to a 4.7nF capacitor tied to ground; this forms a type-2 compensation network with a zero at ~1.5kHz and a pole at ~15kHz, optimizing transient response for 100kHz switching. For the current sense input (pin 3), route the shunt resistor (e.g., 0.1Ω, 1% tolerance) directly from the source of the low-side MOSFET to the pin, keeping traces short to minimize parasitic inductance. Add a 100pF capacitor in parallel to the resistor to dampen ringing from MOSFET turn-off spikes.
Avoid surpassing 1.0V at the current sense pin under full load–exceeding this threshold forces the controller into hiccup mode. If using a coupled inductor, increase the sense resistor value proportionally to the turns ratio to maintain accurate peak current limiting. For isolated designs, opt for a current transformer with a burden resistor matched to the controller’s input impedance (typically 500Ω).
Drive Output and Frequency Setting
Drive the gate pin (pin 6) through a 10Ω series resistor to the MOSFET gate, with a 1kΩ pull-down resistor to ground to ensure rapid turn-off. Use a Schottky diode (e.g., BAT54) across the gate resistor to clamp voltage spikes from gate capacitance. For the oscillator (pin 4), select a 10kΩ resistor and 2.2nF timing capacitor to set a 100kHz switching frequency–critical for minimizing core losses in ferrite inductors. Decouple this pin with a 0.01µF capacitor to ground to suppress supply noise.
Power the controller (pin 7) with a 15V-20V supply, bypassed by a 22µF electrolytic capacitor and a 0.1µF ceramic capacitor in parallel, located within 2mm of the pin. Ground pin 5 directly to a low-impedance star point to prevent ground bounce; use a dedicated plane or thick traces (≥2mm wide) for the return path. If synchronization is required, inject a 3.3V-5V square wave into the RT/CT node (pin 8) via a 51Ω resistor–this locks the frequency to an external master clock without disrupting internal timing.
Step-by-Step Guide to Constructing a Switch-Mode Power Converter Using the 3845 Controller
Select a 24V DC input source with at least 2A current capacity for stable operation. Verify the input voltage with a multimeter before connecting it to avoid overvoltage damage to the MOSFET or inductor. Mismatched input ranges can reduce efficiency or cause thermal failures.
Use a power MOSFET like the IRFZ44N or IRFP250N, rated for 50V/30A minimum. Connect the gate terminal to the PWM output pin (Pin 6) of the controller via a 10Ω resistor to limit inrush current. The drain connects to the inductor, while the source ties to the ground return path. Omitting the resistor risks gate oscillation, leading to erratic switching.
Critical Component Selection
- Inductor (L): Choose a 100μH ferrite-core inductor with a saturation current above 3A. Smaller inductors cause current ripple exceeding 30%, degrading regulation. Verify core material–powdered iron suffices for frequencies below 100kHz; ferrite reduces losses above this range.
- Output Capacitor (Cout): Use a low-ESR 470μF electrolytic capacitor in parallel with a 1μF ceramic capacitor. ESR values above 0.1Ω introduce voltage spikes during load transients. Tantalum capacitors are unsuitable due to high ESR.
- Feedback Network: Implement a 10kΩ resistor (RFB) between the output and the error amplifier (Pin 2) with a 2.5V reference from Pin 1 divided by a 10kΩ resistor. Adjust RFB to 20kΩ for fine-tuning output voltage. Incorrect ratios shift regulation outside ±5%.
Connect the current-sense resistor (Rsense) between the MOSFET source and ground, sized at 0.22Ω. This resistor monitors peak inductor current, triggering cycle-by-cycle overcurrent protection when voltage exceeds 1V. Replace standard metal-film resistors with a shunt resistor for lower thermal drift. Omitting this risks catastrophic failure under overload.
Enable the soft-start function by placing a 1μF capacitor between Pin 8 (Vref) and ground. This ramps the reference voltage over 30ms, preventing output overshoot during startup. For faster response, reduce capacitance to 0.47μF, but monitor for voltage sag under 500mA loads. Polarized capacitors must be oriented correctly–reverse polarity destroys the controller.
Layout and Safety Precautions
- Route high-current traces (MOSFET drain/source, inductor) with 2oz copper pours to minimize resistance and thermal stress. Keep traces under 0.5mm wide for 1A currents; wider traces increase inductance.
- Separate the switching node (MOSFET drain) from feedback traces using a ground plane to reduce EMI. Violations cause erratic regulation or audible noise in the inductor.
- Place a 1N4007 diode across the MOSFET drain-source as a clamp to absorb back-EMF from the inductor. Without it, voltage spikes exceed 100V, damaging the gate oxide.
- Add a 10nF ceramic capacitor from Pin 5 (ground) to the input voltage to filter noise. Larger values introduce instability in the PWM comparator.
Test the output under load using a 10Ω power resistor or an electronic load set to 1A. Measure efficiency at 85% minimum–lower values indicate excessive ESR in the inductor/capacitor or incorrect switching frequency. Fine-tune the feedback resistor if regulation drifts beyond ±2%. For commercial applications, replace the controller’s internal reference with an external 2.5V LDO for tighter tolerance (±1%).
Troubleshooting Common Issues in Flyback Power Supplies with Current-Mode Controllers
Measure the feedback network’s divider resistance first–mismatched values (e.g., R1=10kΩ, R2=2kΩ) skew the error amplifier’s 2.5V reference, causing output voltage drift (±5% or more). Replace resistors with 1% tolerance or recalculate ratios using Vout = 2.5 × (1 + R1/R2). If instability persists, probe the COMP pin with an oscilloscope; spikes >500mV peak-to-peak indicate insufficient compensation. Add a 1nF capacitor across R1 to dampen high-frequency poles, or increase the existing 10nF soft-start capacitor to 47nF for slower ramp-up.
Check for transformer saturation by monitoring primary current with a differential probe during startup–normal slope should be linear up to 2A/μs; a sudden flattening or clipping signals core saturation. Replace the transformer if inductance drops >20% under load, or reduce switching frequency by 20kHz if the original design operates near maximum duty cycle (70-75%). Verify gate drive pulses with >12V amplitude; push-pull drivers weaker than 10V fail to fully enhance MOSFETs, increasing switching losses. Replace the driver IC or add a 10Ω series resistor to the gate to eliminate parasitic turn-on.