IR2112 High and Low Side Driver Circuit Schematic and Functionality Guide
The HVPW2112 device layout demands precise component placement to avoid switching noise. Use a 50Ω gate resistor for MOSFETs below 20A; for higher currents, reduce it to 10-22Ω to balance rise time and overshoot. Bypass capacitors (100nF X7R ceramic) must sit within 2mm of the driver’s power pins–longer traces increase inductive spikes. Ground connections require a star configuration: tie all low-side returns to a single point near the driver’s COM pin, not the power ground.
For half-bridge topologies, isolate the bootstrap diode (1N4148 or faster) from high-frequency paths. A 1μF bootstrap capacitor (X7R) is standard, but for dead-time below 500ns, drop it to 0.47μF to avoid shoot-through. Keep the diode’s cathode trace short; parasitic inductance here causes VBS undershoot during turn-off. If driving IGBTs, add a 10kΩ pulldown on the gate to prevent false triggers from noise.
Thermal management starts with PCB copper: allocate ≥5cm² of 2oz copper for the driver’s thermal pad, even if the device dissipates 60°C, derate the output current by 20%. Avoid placing switching nodes (LO or HO outputs) beneath sensitive analog circuitry–shield them with ground pours or relocate them entirely. Test layouts with a 10MHz bandwidth oscilloscope; noise above 1Vpp on COM or VS nodes indicates poor grounding.
Input logic compatibility requires Schmitt-trigger buffers if the signal source lacks hysteresis. For 3.3V microcontroller interfaces, use a voltage divider on HIN/LIN (e.g., 10kΩ + 20kΩ) to meet the 2.5V logic threshold; omit it for 5V logic. Disable the driver during shutdown by pulling SD high (>2.5V)–floating inputs risk erratic behavior. Verify all connections with a continuity check before power-up; reversed VB and VCC pins destroy the device instantly.
Practical Implementation of the High/Low-Side Driver Layout
Connect the VS pin directly to the source of the low-side MOSFET with a trace no longer than 10 mm. This reduces parasitic inductance and prevents false turn-on during switching transitions. Use a star-point grounding system where the driver’s COM pin and power ground meet at a single node, avoiding shared return paths with high-current loads.
Select bootstrap capacitors between 0.1 µF and 1 µF, depending on switching frequency and gate charge. Ceramic types with X7R dielectric are preferred–avoid electrolytic or tantalum due to slow response times. Place the capacitor within 5 mm of the VB and VS pins, using parallel traces of equal length to minimize loop area.
Critical Power Delivery Paths
- Power rail (VCC): Route as a thick trace, minimum 1 oz copper, with decoupling capacitors (0.1 µF + 10 µF) mounted at the pin entry.
- Gate drive outputs (HO and LO): Keep traces short, wide, and symmetrical to ensure equal propagation delays. Add a series resistor (2–22 Ω) for damping oscillations.
- Bootstrap supply: Isolate from other high-frequency nodes to prevent coupling-induced noise.
For half-bridge configurations, insert a 1 kΩ pull-down resistor on the SD (shutdown) pin to prevent undefined states during power-up. If using PWM inputs, ensure rise/fall times exceed 100 ns to avoid spurious triggering. Optocoupler isolation is recommended when control signals originate from a different ground domain.
Thermal and Layout Precautions
- Avoid placing thermal vias under the driver; heat dissipation should be managed via the exposed pad and adjacent copper pours.
- Minimize crossovers between high-side and low-side drive paths to reduce capacitive coupling.
- Use differential traces for HO and LO outputs if trace length exceeds 15 mm, maintaining 50 Ω impedance where possible.
- Add a 10 V Zener diode across the bootstrap capacitor to clamp voltage spikes exceeding the maximum rating.
Test gate waveforms with a differential probe, verifying less than 2 V overshoot at switching edges. If oscillations persist, increase the gate resistor value incrementally or add a small (1–10 nF) snubber capacitor across the MOSFET drain-source. Apply conformal coating to exposed pads if operating in high-humidity environments.
Key Components Required for High-Voltage Gate Driver Assembly
Select a half-bridge switching IC with isolated high-side output rated for at least 500 V/μs dv/dt immunity and 600 V minimum breakdown voltage–examples include IXYS IXDN609SI or TI UCC21520. Pair it with ultrafast recovery diodes (e.g., STTH1R06D) capable of handling peak reverse voltages exceeding 1.5× the bus voltage and forward current at least 120% of the MOSFET’s ID max.
Critical Supporting Parts
| Component | Specification | Purpose |
|---|---|---|
| Bootstrap capacitor | 0.1–1 μF, X7R ceramic, ≥25 V | Delivers rapid gate charge without droop during 50% duty cycles |
| Isolation resistor | 20–50 Ω, 0.25 W, ±1% | Series with HO/LO pins to dampen 100 MHz+ ringing |
| VDD decoupling | 1 μF + 100 nF, COG, ≥16 V | Prevents VDD collapse during 2 A transient gate currents |
| Dead-time resistor | 4.7 kΩ–10 kΩ, 0.1%, 0.1 W | Sets 50–200 ns gap between high/low transitions |
Add a 12–24 V linear regulator (e.g., ON Semi NCP1117) if logic supply exceeds the driver’s absolute maximum input voltage. Place all passive components within 5 mm of the IC pads to minimize loop inductance–traces wider than 2 mm for currents above 1 A reduce resistive losses. Verify layout symmetry between high-side and low-side paths to balance propagation delays.
Step-by-Step Wiring for High-Side and Low-Side MOSFET Control
Connect the gate driver’s VB pin to a bootstrap capacitor (0.1µF–1µF ceramic, X7R dielectric) between it and the VS pin, ensuring the capacitor’s voltage rating exceeds the supply rail by at least 50%. Route the VS pin directly to the source of the high-side MOSFET with traces no longer than 10mm to minimize inductance. For the low-side MOSFET, tie its source to the ground plane with a dedicated pour, avoiding shared paths with noisy currents like motor returns or switching nodes.
Feed the logic input (typically labeled HIN) from a 3.3V or 5V microcontroller through a 10Ω–100Ω series resistor to dampen ringing. When driving both MOSFETs simultaneously, stagger the activation timing by at least 50ns–activate the low-side first, then the high-side–to prevent shoot-through. Use Schottky diodes (e.g., BAT54) from each gate to its source to clamp negative transients if the driver lacks built-in protection.
Ground the driver’s COM pin to the same star point as the microcontroller’s ground, keeping the connection impedance below 10mΩ. For floating supplies, decouple the VCC pin with a 1µF capacitor placed within 2mm of the pin, using a low-ESR tantalum or a ceramic X5R variant. If parasitic inductance exceeds 20nH in the power loop, add a snubber (10Ω + 0.1µF in series) across the MOSFET drain-source to suppress voltage spikes.
Verify the bootstrap circuit by measuring the voltage across the capacitor with an oscilloscope; it should charge to within 0.5V of the supply during the low-side conduction interval. For frequencies above 100kHz, reduce gate resistor values to 10Ω–22Ω to maintain crisp edge transitions. Use twisted-pair wiring for remote MOSFETs (distance > 5cm) to reduce EMI radiation.
Key Layout Errors in High-Side/Low-Side Driver Designs and Solutions
Place the bootstrap capacitor directly adjacent to the driver IC’s VB and VS pins, no more than 5 mm away. Excessive trace length introduces inductance, causing voltage spikes during switching transitions. Use a ceramic X7R capacitor with 100 nF or higher capacity to ensure stable gate drive voltage under rapid load transients. Test board prototypes with an oscilloscope to verify the bootstrap voltage waveform; ringing above 5% of the nominal voltage indicates layout flaws.
Route high-current paths for the power loop–source to drain of the external MOSFET–on continuous, wide copper pours without sharp corners or narrow necks. A 2 oz copper weight reduces trace resistance by half compared to 1 oz, limiting voltage drops. Keep the loop area minimal to cut parasitic inductance; aim for less than 20 mm² total trace area. For multi-layer boards, align power planes vertically to exploit natural decoupling and reduce EMI from stray magnetic fields.
Separate low-voltage control signals (e.g., input logic, feedback) from switching nodes using ground planes or guard traces. A single via connecting the logic ground to the power ground near the driver IC prevents ground bounce. Avoid routing logic traces parallel to switching nodes; cross them orthogonally. Shield sensitive signals with a continuous ground plane on an adjacent layer, maintaining a clearance of at least 0.5 mm from noisy areas.
Thermal Missteps and Countermeasures
Mount external MOSFETs on dedicated thermal vias–four to six 0.3 mm diameter vias per pad–connected to an internal or bottom-side copper plane. Omit solder mask on the vias to enhance heat transfer. Verify thermal resistance (θJA) with a thermocouple; junction temperature rise above 50°C under 50% duty cycle signals inadequate cooling. Supplement with a 25 mm² heatsink or forced airflow if power dissipation exceeds 1 W.
Decouple the driver’s VCC pin with a 1 µF ceramic capacitor placed within 2 mm of the pin, alongside the bootstrap capacitor. Parallel it with a 10 µF electrolytic to suppress low-frequency noise. Earth both capacitor grounds to the same star point as the power ground to prevent ground loops. Inspect decoupling effectiveness by probing VCC stability; acceptable ripple is below 50 mV peak-to-peak under full load conditions.