Guide to Building and Understanding the AD620 Instrumentation Amplifier Schematic
Begin with a 10 kΩ potentiometer for gain control in your instrumentation amplifier setup. This value balances noise performance and fine adjustment resolution. For ±2.5 V inputs, use a reference voltage at mid-rail (e.g., 1.65 V for 3.3 V supply) to maximize dynamic range while avoiding saturation. Bypass capacitors (0.1 µF) should be placed within 2 mm of the power pins; ceramic types with X7R dielectric prevent high-frequency distortion.
For single-supply operation, tie the negative input pin to a stable reference–a buffered voltage divider (1% tolerance resistors) ensures stability across temperature drifts. Avoid ground loops by routing analog and digital returns separately; star grounding at the power supply minimizes offset errors. When measuring microvolt signals, shield input traces with a guard ring connected to the common-mode voltage to reduce leakage currents.
Gain-bandwidth product limits performance at higher amplifications–at G=100, expect usable bandwidth to drop below 10 kHz. For AC-coupled applications, coupling capacitors (1 µF film types) should be sized to avoid phase shifts at the lowest frequency of interest. Test circuits with a function generator set to 10 mVpp, 1 kHz sine wave; verify output linearity before integrating sensors.
Power supply rejection degrades with unregulated sources–use a low-dropout regulator (e.g., 100 mA capacity) for clean ±5 V rails. For battery-powered designs, add a shutdown pin pull-down resistor (100 kΩ) to conserve power. Calibrate each unit: inject a known 1 mV DC signal, measure output, and trim the potentiometer until error is
Precise Instrumentation Amplifier Assembly: Key Execution Steps
Connect the reference pin (5) to a stable midpoint–typically half the supply voltage–using a low-noise voltage divider for optimal common-mode rejection. Bypass capacitors (0.1µF ceramic) must be placed within 2mm of each power pin (4 and 7) to suppress high-frequency noise; longer traces degrade performance. For gain settings, use precision resistors (1% tolerance or better) with values derived from the formula: G = 1 + (49.4 kΩ / Rg). A 50 kΩ Rg yields G ≈ 2, while 4.99 kΩ achieves G ≈ 11. Keep signal traces on the input stage (pins 2 and 3) symmetrical and under 2cm to minimize parasitic capacitance; differential impedance should match the source (e.g., 1 kΩ for bridge sensors).
Validate the setup with a known input: apply a 10 mVpp, 1 kHz sine wave to pin 3, ground pin 2, and verify the output amplitude scales correctly–distortion below 0.01% confirms proper decoupling and gain accuracy. For battery-powered devices, use a low-dropout regulator (e.g., LT1763) supplying 5V to ensure consistent output swing without clipping. Isolate analog and digital grounds at the power source to prevent ground loops, and route high-impedance nodes away from switching components.
Basic Instrumentation Amplifier Setup and Pin Assignment Guide
The standard gain configuration for this precision device requires only a single external resistor between pins 1 and 8. Calculate the resistor value using RG = 49.4 kΩ / (G – 1), where G is the desired gain. For unity gain (G = 1), leave pins 1 and 8 open–internal 24.7 kΩ resistors already set the default. Ensure resistor tolerance stays below 1% to maintain specified accuracy (±0.05% typical).
Power supply connections must follow: connect +VS to pin 7 and –VS to pin 4. Operating range spans ±2.3 V to ±18 V; however, staying within ±5 V to ±15 V minimizes noise and drift. Decouple each supply pin to ground with a 0.1 μF ceramic capacitor placed within 0.5 cm of the package. Avoid bypassing directly to the load return; use dedicated ground traces instead.
Pin Function Breakdown
- Pin 1 (RG1) and Pin 8 (RG2): Gain resistor terminals. The differential gain equation applies directly here.
- Pin 2 (–IN) and Pin 3 (+IN): High-impedance differential inputs. Impedance exceeds 10 GΩ at DC, enabling direct sensor interfacing without buffering.
- Pin 4 (–VS): Negative supply terminal. Maximum current draw reaches 1.3 mA under ±15 V supply.
- Pin 5 (REF): Reference node. Tie to mid-supply for single-ended output centering or to an external voltage for level shifting. Input impedance sits at 25 kΩ.
- Pin 6 (OUT): Low-impedance output. Drives 10 kΩ loads with less than 1% additional error under full output swing.
- Pin 7 (+VS): Positive supply terminal. Identical current specs to pin 4.
When driving capacitive loads above 100 pF, insert a 50 Ω–200 Ω series resistor between pin 6 and the load to prevent ringing. Output swing typically reaches ±12.5 V under ±15 V supplies before clipping; reduce swing expectations proportionally at lower supplies. Input bias currents stay below ±1.5 nA across the full temperature range, but matching source impedances within 1 kΩ minimizes offset voltage drift.
Common-mode input range extends within 1.1 V of each rail. Exceeding these limits shifts the internal nodes out of saturation, increasing distortion and recovery time. Offset trimming, while optional, uses a 20 kΩ potentiometer between pins 1 and 8 with wiper connected to +VS for positive adjustment or –VS for negative adjustment. Trim range reaches ±200 μV.
Layout considerations dictate star grounding for analog and signal returns. Route input traces away from switching nodes; keep at least 3 mm clearance from digital signals switching above 1 MHz. Thermal gradients across the package should stay below 1 °C/cm to prevent thermocouple effects between pin 2/3 and the die attach pad, which can induce microvolt-level offsets.
Calculating Gain Resistors for Precise Signal Scaling
Select a resistor value using the formula RG = (49.4 kΩ / (G – 1)), where G is the desired gain. For example, a 10x gain requires RG = 5.49 kΩ. Use 1% tolerance resistors to minimize errors; 0.1% tolerance reduces drift to under 0.05% over temperature ranges.
For gains below 10, prioritize low-noise metal film resistors (e.g., Vishay MRA series). At higher gains (50+), thermal noise dominates–choose resistors with a tempco below 25 ppm/°C. Avoid carbon composition resistors; their noise density (1 μV/√Hz) exceeds acceptable limits for sensitive measurements.
Compensating for Parasitic Effects
Lead and trace resistance add errors–calculate their contribution as Rparasitic ≈ 0.1Ω/cm for typical PCB traces. For a 10 cm trace, this adds 1 Ω, skewing gain by ~0.02%. Use Kelvin sensing to cancel this error in high-precision setups, or trim RG experimentally with a 20-turn potentiometer calibrated against a known signal.
Oscilloscope or DMM input impedance (10 MΩ || 12 pF) loads the output. For gains >100, buffer the signal with an op-amp (e.g., OPA2188) to maintain accuracy. Without buffering, loading errors exceed 0.5% at 1 VPP output. For differential signals, ensure RG matches the source impedance within 0.1% to preserve CMRR.
Practical Implementation
For dual-supply configurations (±5 V), verify RG power ratings–dissipation reaches 5 mW at G=10. Use surface-mount devices (e.g., 0805 package) for stability. For single-supply operation (0–5 V), bias the reference pin to mid-supply (2.5 V) and recalculate RG using (Vref × 2) / Ibias. Validate gain accuracy with a 1 kHz sine wave at 100 mVPP; expected error should stay below 0.1% for properly selected resistors.
Power Supply Requirements and Noise Reduction Techniques
Use a dual ±5V regulated supply with a minimum current rating of 10 mA per rail for stable operation. Decouple each power pin with a 0.1 μF ceramic capacitor placed within 2 mm of the pin and a 10 μF tantalum capacitor at the point where the supply enters the PCB. This prevents high-frequency transients from propagating into the system.
Linear regulators like the LM7905/LM7805 outperform switching regulators in noise-sensitive designs, reducing ripple by 60–80 dB at 1 kHz. Place a 1 Ω resistor in series with the input to each regulator to dampen oscillations, followed by a 22 μF electrolytic capacitor on the output. Avoid shared ground paths between analog and digital sections–use a star-ground topology with a single reference point near the power supply.
Shield sensitive traces with ground planes on adjacent layers, maintaining a clearance of at least 0.5 mm from high-speed or noisy signals. For differential pairs, ensure trace lengths match within 5 mm and maintain a controlled impedance of 100 Ω ±10%. Ferrite beads (e.g., Murata BLM18PG121SN1) on supply lines suppress noise above 1 MHz with minimal DC resistance.
| Component | Value | Placement |
|---|---|---|
| Ceramic capacitor | 0.1 μF | ≤2 mm from IC pin |
| Tantalum capacitor | 10 μF | Power entry point |
| Ferrite bead | BLM18PG121SN1 | Series with V+ and V– |
| RC filter | 10 Ω + 1 μF | Output stage |
Thermal noise from resistors can dominate low-level signals. Use metal-film resistors with 0.1% tolerance and a noise index of ≤0.2 μV/V. Place a 100 nF capacitor across gain-setting resistors to bypass noise to ground. For signal paths, avoid vias under components–route traces on the top layer only where possible to minimize parasitic capacitance.
When using batteries, NiMH cells provide lower noise than alkaline, with a self-discharge rate of 1–2% per day. For mains-powered designs, a toroidal transformer (e.g., Triad Magnetics VPT16-1000) reduces magnetic coupling with external fields. Add a Schottky diode (BAT54) antiparallel to each supply rail to clamp inductive spikes, preventing latch-up conditions.
Grounding Strategies
Avoid daisy-chaining ground connections. Separate analog, digital, and power grounds, connecting them only at a single point near the power supply. For mixed-signal systems, use an isolation gap of ≥1 mm between ground planes and route signals perpendicular to the gap to minimize cross-talk. Test grounding integrity with a 100 Hz, 1 mA current injection–voltage drop between any two ground points should not exceed 10 μV.