IR2153 Control Circuit Schematic and Working Principle Breakdown

ir2153 circuit diagram

For half-bridge topologies requiring 10–500 kHz switching, a dedicated gate driver IC delivers optimal performance with minimal component count. The tested configuration operates from a 12–24 VDC input, drives MOSFETs or IGBTs up to 600 V, and achieves 92% efficiency at 150 kHz with 100 Ω load. Begin with a 1 μF bootstrap capacitor–values below 0.47 μF cause premature UVLO triggering under 30% duty cycles.

Place the high-side gate resistor directly between the driver output and MOSFET gate terminal, ideally within 5 mm, to suppress ringing. For fast-switching SiC MOSFETs, reduce this resistor to 5–10 Ω; standard silicon devices tolerate 15–35 Ω. Always decouple VCC with a 100 nF ceramic capacitor in parallel with a 10 μF electrolytic, positioned no farther than 2 cm from the driver IC to prevent voltage sag during current transients exceeding 2 A.

For 400 V bus applications, insert a 20 Ω series resistor on the bootstrap diode’s anode to limit inrush current to 250 mA, preserving diode lifespan. If dead-time exceeds 500 ns, add a 47 kΩ pull-down resistor on the shutdown pin to prevent false triggering–critical when driving inductive loads with >1 mH inductance. Avoid capacitor types with ESR above 100 mΩ in the bootstrap path; X7R ceramics or film capacitors ensure reliable charging down to -40°C.

To synchronize multiple drivers, route a low-inductance ground plane linking all ICs and ground-referenced capacitors–trace inductance above 10 nH causes cross-conduction spikes exceeding 5 V. For EMI compliance, shield gate traces with adjacent ground returns and apply a 1 nF snubber across each switch node when slew rates exceed 10 V/ns. Verify layout with a 10:1 oscilloscope probe; common-mode noise above 200 mVpp indicates insufficient decoupling or routing errors.

Practical Implementation of the Self-Oscillating Driver Layout

Connect the high-voltage bootstrap capacitor between VB and VS pins, using a 0.1µF ceramic rated for 50V minimum–ceramics avoid leakage currents that electrolytics introduce, skewing dead-time. Position the capacitor no farther than 5mm from the chip leads; any stray inductance above 10nH will trigger false commutation during switch-node slew rates exceeding 5V/ns.

For gate drive traces, maintain 50-ohm impedance by keeping traces under 10mm length and 0.5mm width; wider traces increase capacitive coupling to adjacent copper pours, distorting rise times measured at HO/LO outputs. Terminate HO/LO outputs with 10Ω series resistors to combat gate ringing–pre-molded gate resistors with 1W power rating prevent solder cracking during 2A repetitive pulses. Ensure the switch-node copper fills an area no smaller than 50mm² to dissipate 3W thermal load at 200kHz operation.

Fault Protection and Load Integration

Route SD pin to a 5.1kΩ pull-down resistor grounded through a 2N7000 MOSFET; this configuration blocks false shutdown during 120Hz ripple on the VCC rail exceeding ±10%. Place a 1nF snubber directly across drain-source terminals of power MOSFETs to suppress 60V spikes that otherwise exceed dv/dt immunity thresholds–polypropylene film capacitors outperform X7R dielectrics here due to lower ESR at frequencies above 1MHz.

Basic Driver IC Pinout and Common Hookups

Always start by verifying the high-side and low-side gate outputs at pins HO (7) and LO (5) against the input signal at RT/CT (2). Ensure the bootstrap capacitor connects directly between VB (8) and VS (6)–use a 100 nF, 25 V-rated ceramic capacitor for reliable floating supply generation. Avoid longer traces between these pins to prevent voltage spikes that disrupt switching.

For timing control, RT/CT (2) requires an external resistor-capacitor network. A typical 10 kΩ resistor and 1 nF capacitor yield ≈50 kHz oscillation. Adjust values symmetrically–matching resistors on RT (1) ensure dead-time consistency. Misalignment here introduces shoot-through risk, degrading efficiency by up to 15%.

Critical External Connections

  • VCC (3): Supply 10–20 V here, bypass with a 10 µF electrolytic capacitor in parallel with a 100 nF ceramic cap to filter noise.
  • COM (4): Tie this to the system ground plane. Avoid sharing this trace with high-current paths to minimize ground bounce.
  • Bootstrap Path: The diode between VCC (3) and VB (8) must handle the full switching current–use a 1 A, 50 V Schottky diode for low forward drop.

Power stage layout demands precision: place the bootstrap capacitor adjacent to VB (8) and VS (6), with no vias interrupting the return path. High-side MOSFET source (VS) should connect to the load midpoint via a wide, low-inductance trace to reduce stray inductance. Failure to observe this causes voltage overshoot exceeding 50% of the rail, risking component damage.

For input conditioning, decouple RT/CT (2) with a 100 nF capacitor to suppress high-frequency noise. If using an external oscillator, disable the internal one by pulling RT (1) high (above 2.5 V). Disable dead-time control by connecting DT/SD (9) to COM (4) for default 1 µs dead-time; override only with careful timing analysis.

  1. Verify VCC (3) stability before applying input signals–unstable supply triggers erratic switching.
  2. Use twisted-pair wiring for HO and LO gate outputs if driving MOSFETs >5 cm away to limit EMI.
  3. Thermal management: Solder the IC’s exposed pad (if present) to a copper pour tied to COM (4) for heat dissipation.

Step-by-Step Wiring for Half-Bridge Driver Assembly

Begin by connecting the high-side MOSFET gate to output pin HO of the control IC (pin 5). Use a 10Ω series resistor to limit gate charge current and prevent ringing. Ensure the MOSFET’s source ties directly to the switching node, avoiding trace loops longer than 5mm. The bootstrap capacitor (100nF, 25V X7R ceramic) must sit within 2mm of pin VB (pin 8) and VS (pin 6), with its negative terminal soldered to VS.

Ground the low-side MOSFET gate to output pin LO (pin 7) via another 10Ω resistor. Link its drain to the switching node–same node as the high-side MOSFET’s source–and connect its source to the negative rail (ground). For the timing network, attach a 10kΩ resistor between RT (pin 2) and ground, and a 1nF capacitor between CT (pin 3) and ground. Adjust RT for frequencies between 20kHz–60kHz; values lower than 8kΩ risk IC damage.

Critical Power Supply Connections

  • Feed VCC (pin 1) with 12–15V DC via a 100μF electrolytic capacitor (low ESR) placed ≤10mm from the pin. Include a 1N4007 diode in series to block reverse voltage.
  • Bypass VCC to ground with a 1μF X7R ceramic capacitor (
  • Isolate the negative rail (ground) of the control section from power ground using a single-point star connection at the IC’s GND (pin 4).

Route the output load between the switching node and the negative rail, through a 10μH inductor (core saturation >2A) and a 100μF/25V capacitor in parallel. Keep traces thick–≥2mm for currents exceeding 1A–and minimize sharp angles to reduce EMI. Test with an oscilloscope: HO/LO signals should show

Fault Prevention Checks

  1. Verify the bootstrap capacitor charges to ~VCC-0.7V within 10μs of startup; slower charging suggests excessive load capacitance or incorrect VS-VB routing.
  2. Confirm the switching node never lingers between high and low states (>200ns dead-time ensures shoot-through protection).
  3. Measure quiescent current (

Calculating Resistor and Capacitor Values for Self-Oscillating Driver Stages

To determine the timing components for a half-bridge driver’s internal oscillator, start with the desired operating frequency. The formula f = 1 / (1.4 × R × C) applies, where R (in ohms) and C (in farads) define the charge-discharge cycle. For a 50 kHz target, use R = 10 kΩ and C = 1.5 nF as a baseline–these values yield roughly 47.6 kHz, balancing dead-time and switching losses. Adjust R upward if gate drive strength suffers at higher frequencies.

Dead-time between high- and low-side outputs depends on C‘s discharge path. The internal 0.5×VDD threshold imposes a fixed dead-time of ~600 ns per nanofarad of timing capacitance. Reduce C to shorten dead-time but ensure C ≥ 470 pF to prevent erratic triggering from noise. For precision, measure actual dead-time with an oscilloscope–most designs tolerate 200–800 ns without shoot-through risks.

Gate resistor selection impacts rise/fall times and power dissipation. For MOSFETs with Qg ≤ 30 nC, use Rg = 10–47 Ω; higher values smooth transitions but increase switching losses. Boost-load applications benefit from Rg = 22 Ω, while low-power setups can drop to Rg = 5.1 Ω for faster edges. Bypass Rg with a 100 nF X7R ceramic capacitor to suppress voltage spikes.

Stability under varying loads requires a bootstrap capacitor sized for worst-case hold-up. The rule Cboot ≥ 10 × Qg / (Vboot – Vf) ensures adequate gate charge, where Vf is the diode forward drop. For a 12 V supply and Qg = 20 nC, Cboot = 220 nF (50 V rating) suffices. Choose a fast-recovery diode (e.g., 1N4148) to minimize bootstrap recharge time.

Temperature drift affects oscillator frequency–use 1% tolerance resistors and C0G/NP0 capacitors for stability. If ambient swings exceed ±25°C, recalculate R and C at extremes: a 10 kΩ resistor may shift ±5%, while X7R capacitors can vary ±15%. For critical applications, add a 10 kΩ trimpot in series with R to fine-tune frequency post-assembly.

Power Supply Requirements and Bootstrapping in Self-Oscillating Gate Drivers

Use a floating supply ranging from 10V to 20V for the high-side driver to ensure reliable gate turn-on without latch-up risks. The low-side driver operates directly from the VCC pin, requiring 11.5V–15V for optimal performance–voltages below 10V may cause erratic switching, while exceeding 20V risks gate oxide degradation. For bootstrapping, employ a fast-recovery diode (e.g., UF4007) with a reverse recovery time ≤75ns and a 100nF–1µF high-frequency ceramic capacitor rated for at least 25V. Avoid electrolytics due to their high ESR, which introduces voltage sag during peak currents.

Calculate bootstrap capacitor size using Cboot = Qg / ΔV, where Qg is the gate charge of the MOSFET (typically 20–100nC) and ΔV is the allowed voltage drop (0.5V–1V). For a 50nC gate charge and 0.7V drop, Cboot = 71nF–round up to the nearest standard value (e.g., 100nF). Below 20kHz switching frequencies, increase capacitance by 20–30% to compensate for leakage currents. Below is a reference table for common MOSFET gate charges:

MOSFET Type Gate Charge (Qg) Min. Cboot (ΔV=0.7V) Recommended Cboot
IRFZ44N 42nC 60nF 82nF
IRFP460 120nC 171nF 220nF
IXFH60N60 85nC 121nF 150nF

Grounding and Parasitic Inductance Mitigation

Star-ground the driver’s COM pin and MOSFET source terminals to minimize ground bounce, which can exceed 2V at turn-off transients in layouts exceeding 5cm trace lengths. For the bootstrap diode, position it within 10mm of the capacitor to reduce loop inductance–longer paths increase dV/dt spikes, false triggering, or latch-up. Add a 1–10Ω series gate resistor to dampen oscillations caused by parasitic inductance (typically 5–15nH in SOIC-8 packages). For switching frequencies above 100kHz, use a 1N4148 diode in parallel with the gate resistor to clamp negative overshoot.