Sony Multiplex Signal Demux 19 kHz Low Pass Filter Circuit Schematic Guide
For optimal signal clarity in stereo signal processing, implement a third-order Bessel topology with a cutoff at 18.9 kHz (±0.1 kHz). This configuration minimizes phase distortion while maintaining sufficient roll-off (≈18 dB/octave) to isolate pilot tones. Use 1% tolerance polyester capacitors (values: 470 pF, 1 nF, 4.7 nF) and metal film resistors (10 kΩ, 22 kΩ, 47 kΩ) to ensure thermal stability.
Ground the circuit via a star configuration, connecting all reference points to a single analog ground plane to reduce crosstalk. If handling signals above 2 Vpp, add a clamping diode pair (1N4148) at the input to prevent overload. Test with a precision sine wave generator at 19 kHz (±100 Hz) and verify on the output.
For PCB layout, maintain symmetrical trace lengths (feedback network (22 pF + 4.7 kΩ) as close as possible to the op-amp (TL072/NE5532) to minimize stray capacitance. Power the circuit with ±12V regulated supply, decoupled with 100 nF ceramics on both rails.
When calibrating, adjust the series resistor (1.5 kΩ trimpot) in the output stage to match the group delay (±50 µs) across the passband. If distortion exceeds low-noise FET-input model (e.g., OPA2134). For automated testing, use a swept frequency analyzer (15 kHz–22 kHz) with logarithmic sweep rate of 1 kHz/sec.
Constructing a 19,000 Hz Signal Separator Circuit
Begin with a second-order Sallen-Key topology to achieve sharp attenuation beyond 19 kHz. Use a quad operational amplifier IC (e.g., TL074) with ±12V rails for optimal headroom. Place a 1 nF capacitor between the non-inverting input and ground, then pair it with a 22 kΩ resistor in series to set the cutoff frequency. Feedback components–1 nF capacitor and 22 kΩ resistor–mirror the input values to maintain unity gain and precise corner frequency.
The component selection impacts stability and noise performance. Film capacitors (polypropylene or polystyrene) outperform ceramic types due to lower dielectric absorption and superior high-frequency behavior. For resistors, metal-film types with 1% tolerance ensure consistency. Avoid carbon-film resistors; their higher noise floor degrades signal integrity in audio applications. Verify the circuit on a solderless breadboard first, then transition to a PCB with ground planes to minimize interference.
| Component | Value | Type |
|---|---|---|
| Op-Amp IC | TL074 | Quad, JFET-input |
| Capacitor | 1 nF | Polypropylene |
| Resistor | 22 kΩ | Metal-film, 1% |
| Supply Rails | ±12V | Linear regulator |
Test the circuit with a dual-channel oscilloscope and function generator. Inject a 1 Vpp sine wave at 18 kHz; the output should remain within 0.5 dB of the input. At 20 kHz, expect at least 12 dB roll-off. If attenuation is insufficient, swap the 22 kΩ resistors for 18 kΩ units to shift the cutoff downward. Alternatively, increase capacitor values to 1.2 nF for a gentler slope. Document each adjustment to refine the response curve.
For stereo implementations, duplicate the single-channel circuit but share the supply rails between channels. Decouple each op-amp’s power pins with 100 nF capacitors to ground, placed as close as possible to the IC. Route signal traces away from digital lines; even weak coupling from a nearby microcontroller can introduce aliases around 19 kHz. Enclose the final assembly in a shielded metal case if operating in environments with high RF noise.
Calibrate the circuit using a spectrum analyzer. Adjust the resistor-capacitor pairs in 5% increments until the roll-off aligns with the target specification. Record the final values–small deviations can push the cutoff above 19,500 Hz or below 18,500 Hz, affecting pilot tone separation in FM applications. Once optimized, etch a PCB with precise trace widths to preserve impedance consistency; a 0.254 mm trace width suits 50 Ω paths for this frequency range.
Key Elements of a 19,000 Hz Signal Attenuation Circuit in Broadcast Separation Units
Begin by selecting a precise cutoff frequency resistor-capacitor pair to isolate subcarrier signals without phase distortion. For a 19,000 Hz boundary, use a 470 pF capacitor with a 18 kΩ resistor–this combination ensures a –3 dB point at the exact threshold while minimizing ripple in the stopband. Adjust values in 5% increments to fine-tune roll-off characteristics based on board trace capacitance.
Incorporate an active amplification stage before filtering to compensate for insertion loss. A single-op-amp topology with unity gain (e.g., TL072) preserves amplitude integrity, while a feedback loop set at 2× the corner frequency prevents oscillations. Avoid passive networks here–signal degradation at this stage directly impacts stereo separation accuracy downstream.
Shield sensitive traces with grounded copper pours beneath the RC network. A 30 mil spacing between input/output lines and adjacent digital signals reduces crosstalk to below –80 dB. For multilayer boards, place the attenuation circuit on an inner layer adjacent to a solid ground plane to eliminate high-frequency interference from switching regulators.
Critical Component Tolerances
- Capacitors: ±2% C0G/NP0 dielectric to prevent temperature drift beyond ±30 ppm/°C.
- Resistors: ±1% metal film for stable impedance across the operational temperature range (–20°C to +70°C).
- Op-amps: Slew rate ≥10 V/μs to handle transient peaks without slew-induced distortion.
Add a ferrite bead (e.g., Murata BLM18PG121SN1) in series with the input to suppress RFI above 50 MHz. This element should precede the RC stage to prevent aliasing artifacts that would otherwise pass through the cutoff boundary. Verify bead impedance at 100 MHz (target ≥100 Ω) to ensure effective noise suppression without introducing excessive series resistance.
Test the circuit’s step response with a 1 Vpp, 19,000 Hz square wave. Optimal performance yields
For power supply decoupling, place a 100 nF X7R capacitor within 2 mm of the op-amp’s VCC pin, bypassed by a 10 μF tantalum capacitor. This pairing suppresses high-frequency noise (>1 MHz) while handling low-frequency ripple. Omit either component, and instability may manifest as 1–3 dB gain variations at the threshold frequency.
Troubleshooting Checklist
- Measure actual corner frequency with an FFT analyzer–deviations >5% require recalibration.
- Probe for DC offset at the output (must be
- Verify load impedance matches the filter’s output impedance (≤1 kΩ) to avoid frequency response skewing.
Assembling a 19,000 Hz Signal Attenuator on a Prototyping Board
Begin by arranging the required components on the workspace: a 100 nF ceramic capacitor, a 4.7 kΩ resistor, and a solderless breadboard. Identify the circuit’s input and output nodes from the reference layout–typically marked by a signal source pad and a load connection. Place the resistor vertically between the two horizontal power rails, ensuring one lead connects directly to the incoming signal path. The capacitor follows, inserted parallel to the resistor’s other terminal, bridging the signal path to the ground rail.
- Verify component values with a multimeter before insertion.
- Use short, straight jumper wires to minimize parasitic effects.
- Avoid bending leads excessively–this risks fractures in the resistor film or capacitor dielectric.
Power the setup with a regulated 5 V supply. Probe the output node with an oscilloscope; a properly configured network will suppress frequencies above 18,900 Hz by at least 3 dB. If attenuation deviates, swap the resistor for a 3.3 kΩ or 10 kΩ variant–the cutoff shifts downward or upward, respectively. For sharper roll-off, substitute the capacitor with a 220 nF unit.
Test different signal amplitudes (0.1 V to 2 V peak-to-peak). Attenuation consistency across this range confirms linear operation. Document measurements at 15,000 Hz, 20,000 Hz, and 25,000 Hz for baseline comparison. If unwanted oscillations appear, add a 1 kΩ resistor in series with the input–this dampens reactive overshoot without altering cutoff behavior.
Calculating and Selecting Resistor-Capacitor Combinations for Precise Signal Attenuation
For a 19 Hz cutoff, pair a 1 kΩ resistor with a 8.2 μF electrolytic capacitor. This combination yields a -3 dB point at approximately 19.4 Hz, confirmed by fc = 1/(2πRC). Non-polarized alternatives include 0.1 μF film capacitors with 82 kΩ resistors for identical response, though phase shift characteristics differ slightly–polypropylene offers tighter tolerance (±1%) than polyester (±5%).
To achieve a sharper roll-off, cascade two identical RC stages. The second stage load impedance must exceed the first by 10× to prevent interaction; for instance, use 10 kΩ and 1 μF followed by 100 kΩ and 0.1 μF. This arrangement doubles theoretical slope to -40 dB/decade but introduces 6 dB insertion loss at the cutoff frequency–compensate with a gain stage no closer than 3× the first resistor value.
Component Variability and Practical Adjustments
Commercial resistors exhibit ±1% or ±5% tolerance; capacitors range ±1% (NP0/C0G) to ±20% (X7R/Z5U). For 19 Hz, the error margin grows if R=100 Ω and C=82 μF–±5% in R and ±10% in C produce ±15% cutoff variance. Mitigate this by selecting 1% metal-film resistors and ±2% NP0 capacitors, narrowing deviation to ±3 Hz. Temperature drift (NP0: 30 ppm/°C) remains negligible below 50°C.
In high-impedance circuits, stray capacitance (typically 3–5 pF) alters cutoff. A 1 MΩ resistor with 8.2 pF stray capacitance unintentionally forms an 18 kHz high-frequency roll-off. Guard rings or Teflon standoffs reduce this effect to 0.3 pF. Alternatively, reduce impedance–10 kΩ resistors see stray effects only above 16 MHz, well beyond audio bandwidth.
Parasitic Inductance and Layout Considerations
Lead inductance in electrolytic capacitors (≈5 nH/mm) becomes significant above 100 kHz. For sub-20 Hz applications, this is irrelevant, but PCB traces longer than 2 cm introduce series inductance, forming unintended LC networks. Keep traces short and wide (1 mm width per 1 A), or use SMD components–0805 resistors and 1206 capacitors exhibit <1 nH inductance. Vias add ≈0.5 nH each; minimize their count near the RC pair.
Avoid placing the capacitor near switching regulators or digital lines. Ripple currents couple through parasitic capacitance (≈0.1 pF/cm for parallel traces), modulating the cutoff frequency. Separate analog and digital ground planes, connecting them at a single point adjacent to the capacitor. For bipolar supplies, split the ground return–negative terminal directly to star ground, positive through a ferrite bead (600 Ω at 1 MHz).
For variable cutoff tuning, replace the resistor with a 100 kΩ multi-turn trimpot (Bourns 3296) and a 1 μF film capacitor. The adjustment range spans 1.6 Hz to 16 kHz with a single potentiometer. Calibrate using a signal generator and oscilloscope: set input amplitude to 1 Vpp, adjust trimpot until output reads 0.707 Vpp. Lock the setting with thread locker to prevent drift from vibration.