Detailed Circuit Diagram Analysis of Tny278pn Switched Mode Power Supply
For optimal performance in off-line switcher designs, position the line-side filter components within 5mm of the primary input terminals. Use X2-class capacitors rated for 275VAC with a minimum capacitance of 0.1µF to meet IEC 60384-14 surge requirements. Space the EMI choke at least 10mm from the switching element to prevent parasitic coupling–ferrite cores with AL values between 2000–4000 nH/turn² work best for this topology.
Place the flyback transformer on the underside of the board, directly opposite the controller IC, to minimize trace inductance. Wind the primary with 5–7 turns of 0.5mm enameled wire, ensuring a leakage inductance below 10µH measured at 100kHz. The secondary output must use ultra-fast recovery diodes (trr < 35ns) with a repetitive peak reverse voltage of 100V for 5V outputs and 200V for 12V rails.
Thermal management requires a solder pad of at least 300mm² for the device’s tab, connected to a 2oz copper pour via multiple 1mm vias. The feedback network should employ a precision shunt regulator (e.g., TL431) with a 0.1% tolerance resistor divider for ±2% output accuracy under full load. Decouple the control pin with a 1µF ceramic capacitor (X5R/X7R dielectric) located within 2mm of the pin to suppress high-frequency noise.
Input voltage sensing demands a 1MΩ resistor in series with a 470pF snubber capacitor across the primary winding. This combination reduces voltage spikes to less than 700V under maximum input conditions (265VAC). For output isolation, maintain a creepage distance of ≥8mm between primary and secondary circuits–achieve this by routing traces on opposite layers with a 1mm gap or using a slot in the PCB substrate.
Active load regulation requires a current-sense resistor of 0.2Ω for 1A outputs, selected for a pp at 100kHz with a 10% load step.
Designing Power Solutions with TNY Series ICs
Start by selecting a primary-side regulated switcher IC with an integrated 700 V MOSFET within the DIP-8 package footprint. Confirm the chosen model supports input ranges from 85 to 265 VAC while delivering up to 28 W output–ideal for isolated flyback configurations. Use a 1 μF Y1 safety capacitor between the primary and secondary grounds to suppress common-mode noise, adhering to IEC 60384-14 standards.
Critical component placement:
- Position the input filter capacitor (minimum 10 μF, 400 V) no farther than 10 mm from the IC’s DRAIN pin to minimize switching spikes.
- Place the bias winding capacitor (22 μF, 35 V) directly across the BYPASS and SOURCE pins, ensuring traces remain under 5 mm to reduce parasitic inductance.
- Terminate the feedback winding through a 1 MΩ resistor and 1N4007 diode, connecting the node to the FEEDBACK pin for accurate voltage sensing–avoid sharing this trace with high-current loops.
For output regulation, employ a TL431 shunt regulator driving an optocoupler (e.g., PC817) with a 1 kΩ series resistor on the secondary side. Set the output voltage via a voltage divider: use a 10 kΩ resistor from the cathode to ground and a 120 kΩ resistor from the cathode to the output rail–this yields 12 VDC within ±2% tolerance under full load (2 A). Verify transient response by loading the output with a 10 μF ceramic capacitor; undershoot should not exceed 2 V for 1 ms.
Thermal management dictates PCB layout: allocate a 2 oz copper pour under the IC extending at least 20 mm beyond the outline, stitching it to internal planes with thermal vias (0.3 mm diameter, spaced 1.5 mm apart). Heat dissipation must limit junction temperature to 125°C–calculate power loss using PD = IDRAIN2 × RDS(ON) (typical 2.3 Ω at 25°C) and derate by 30% for ambient temperatures above 85°C. For EMI compliance, insert a 1.5 kΩ resistor in series with the DRAIN pin along with a 10 nF snubber capacitor to dampen ringing above 1 MHz.
Debugging steps:
- Measure the EN/UV pin voltage: must exceed 1.5 V under normal operation–values below 0.8 V indicate undervoltage lockout.
- Inspect the feedback waveform at the optocoupler collector using a 10x probe; rise times should be sub-1 μs–slower edges suggest insufficient bias winding capacitance.
- Check for excessive power dissipation: if surface temperature exceeds 100°C, reduce input voltage or increase heat sink area–alternatively, switch to a higher-current model rated at 650 mA.
Identifying Pin Configuration and Power Requirements
Locate the datasheet for the IC to decode pin assignments–manufacturers define VIN, GND, SW, FB, and enable pins differently. Cross-reference markings on the package with the sheet: a dot or notch typically marks the first pin, progressing counterclockwise. Verify pin numbering against package type (SOIC-8, SOT-23, etc.), as physical layouts vary.
Measure input voltage range with a multimeter before connecting power. Most switching regulators tolerate 9–36V, but transient spikes exceeding absolute maximum ratings (usually 40V) destroy the IC. Use a bench supply with current limiting set at 20% above expected load to prevent thermal runaway during initial testing.
| Pin Label | Typical Function | Voltage Range (V) | Critical Notes |
|---|---|---|---|
| VIN | Power input | 9–36 | Bypass with 10μF MLCC + 1μF ceramic |
| GND | Reference ground | 0 | Star-point connection; avoid noise coupling |
| SW | Switching node | −0.3 to VIN + 0.3 | Connect inductor here; keep traces short |
| FB | Feedback input | 0.8–3.3 | Requires resistive divider for regulation |
Calculate power dissipation using P = IOUT × (VIN − VOUT) × duty cycle. For a 5V output at 2A with 24V input, dissipation reaches ~4W–exceeding package limits (typically 1.5W) without a heatsink. Add a copper pour (25mm2 minimum) on the PCB to enhance thermal performance.
Select input/output capacitors based on ripple current ratings. Input capacitors must handle RMS current equal to IOUT × √(D × (1 − D)), where D is the duty cycle. Aluminum electrolytic capacitors (220μF/50V) often fail under high ripple; pair with low-ESR ceramics (X5R/X7R) for stability.
Check the feedback network: a 1% tolerance resistor divider ensures output accuracy. For a 3.3V target, use R1 = 22.1kΩ and R2 = 10kΩ. Connect FB directly to the output node–parasitic capacitance on long traces (>10mm) introduces overshoot. Add a 10–100pF ceramic capacitor across R1 to dampen oscillations.
Enable pins (EN, BP) often have pull-up resistors tied to VIN–measure voltage levels before soldering. A floating EN pin causes erratic startup; a 100kΩ resistor ensures reliable activation. For under-voltage lockout, add a Zener diode (e.g., 12V) from EN to GND to prevent operation below minimum input thresholds.
Step-by-Step Guide to Assembling a Flyback Power Stage with the TNY Series
Select a high-voltage MOSFET with a 650V breakdown rating and on-resistance below 4Ω to minimize conduction losses. Position the transistor as close as possible to the primary winding connection point, reducing parasitic inductance. Use a direct copper pour on the PCB for the drain path to improve thermal dissipation.
Wind the primary coil with 22 AWG magnet wire, ensuring 30–35 turns for a 12V output at 2A. Space turns evenly to prevent voltage stress concentrations, and insulate each layer with polyimide tape if layer count exceeds two. The secondary requires 5–6 turns of 18 AWG wire, split into two parallel strands for lower skin-effect losses.
Place the feedback network within 2mm of the controller’s feedback pin to avoid noise pickup. Use a 1N4148 diode in series with a 4.7kΩ resistor for bias, and couple the output to the feedback pin via a 220nF capacitor. Avoid ground loops by routing the feedback return path directly to the source pad of the MOSFET.
Attach a 10Ω/1W ceramic resistor in series with the startup capacitor (typ. 22μF/50V) to limit inrush current. The resistor’s placement should be adjacent to the VDD pin, with a 1μF/50V bypass capacitor soldered directly across the VDD and source terminals to suppress high-frequency noise.
For snubber design, pair a 2.2nF/1kV ceramic capacitor with a 47Ω/2W resistor in series. Mount the snubber across the primary winding’s terminals, not the MOSFET’s drain-source gap, to reduce ringing without increasing switching losses. Verify snubber effectiveness by measuring peak drain voltage–target under worst-case load conditions.
Use a shunt regulator (TL431) with a 10kΩ voltage divider for precise output regulation. Position the divider resistors on the underside of the board, directly beneath the TL431, to shorten feedback traces. Add a 100pF capacitor from the reference pin to ground to stabilize the control loop.
Oscilloscope probing requires 10x attenuation and ground-spring adapters to avoid false readings. Probe the MOSFET’s gate during startup–rise time should be . If overshoot exceeds 10% of input voltage, increase the gate-series resistor (typ. 22Ω–47Ω) incrementally while monitoring efficiency impact.
Common Pitfalls in Designing the TNY-Based Power Layout
Avoid neglecting the input capacitor placement. Positioning it more than 2 cm from the primary-side controller’s pinout causes excessive voltage ripple, reducing efficiency by up to 12%. Always mount it adjacent to the high-voltage input terminal, using a low-ESR ceramic (X7R or X5R) with at least 4.7 µF capacity.
Misconfiguring the feedback network leads to instability. The optocoupler’s collector resistor must match the controller’s internal current sink–2 kΩ for 2 mA nominal feedback. Deviating by ±10% triggers erratic switching or excessive output overshoot (>5% of nominal load). Verify the LED current with a precision ammeter during prototype testing.
Overlooking transformer winding polarity results in destructive voltage spikes. The primary and secondary must use a dot convention; reversing the secondary coil’s start/end points induces leakage inductance peaks exceeding 200 V, violating the MOSFET’s 700 V breakdown limit. Use an oscilloscope to confirm
Incorrect snubber design wastes power. Resistor values beyond 470 Ω or capacitor sizes below 470 pF (for 130 kHz operation) fail to suppress EMI, increasing conducted emissions by 6 dB. Measure snubber dissipation; if it exceeds 100 mW, recalculate using the leakage inductance value from the transformer datasheet.
Key Error: Undersized Output Capacitors
Choosing output capacitors solely by voltage rating causes load transient failures. A 10 V, 22 µF tantalum capacitor may meet voltage requirements but sag 1.2 V under 300 mA load steps due to insufficient ripple current rating. Replace with polymer types rated for ≥1 A ripple, or parallel multiple 10 µF ceramics. Verify ESR compliance using an impedance analyzer at 100 kHz.
Skipping the bias winding compromises light-load efficiency. The auxiliary coil must deliver 8–14 V to the controller’s VCC pin; omitting it forces start-up from the main input, increasing no-load consumption from 5 mW to 25 mW. Ensure the winding turns ratio matches the output voltage (e.g., 3:1 for 5 V output), and use a 1N4148 diode for rectification.
Improperly routed ground traces introduce noise. Star-point grounding is mandatory: connect the input capacitor, output capacitor, and controller GND to a single node. Separate signal and power planes; traces longer than 10 mm between these points act as antennas, amplifying 50–150 kHz switching noise by 3 dB. Use a 4-layer PCB with dedicated ground planes to minimize impedance.
Disregarding thermal derating shortens component lifespan. The controller’s SO-8 package dissipates 600 mW at 70°C ambient; exceeding this causes junction temperatures above 125°C, reducing MTBF by 40%. Attach a 10 mm² copper pour to the exposed pad and verify thermal resistance with a calibrated infrared thermometer. Forced air cooling (200 LFM) lowers θJA from 65°C/W to 40°C/W.