Class AB 35MHz 70W Linear Amplifier Circuit Design and Schematics Guide

Start by sourcing two IRF510 MOSFETs or their closely matched counterparts (e.g., IRFP250) arranged in a push-pull emitter-follower configuration. This topology delivers 65–75 W continuous sine-wave output into a 50-Ω load with a single 30–36 VDC rail, while keeping harmonic distortion under −40 dBc at full drive. Keep the gate drive circuitry simple: use a center-tapped RF transformer (1:2 voltage step-up) at the input, wound on a Fair-Rite 2643000102 binocular core or equivalent, ensuring the primary sees a low impedance source to prevent parasitic oscillations.

Place 47 pF silver-mica capacitors directly at each MOSFET gate lug to ground; omit this step and expect instability above 1 W input. Bias the gates via a 10 kΩ potentiometer wired between the +VDC rail and a 1 N4148 diode string that sets approximately 2.5 VDC at the potentiometer wiper–this guarantees class-B crossover distortion remains inaudible during SSB modulation. For thermal stability, mount both devices on a shared heatsink with at least 1 °C/W rating and apply thermal compound rated for >150 °C; runs exceeding 20 minutes at full power require forced-air cooling.

Insert a dual-pi-network low-pass filter immediately after the drain output capacitors to suppress harmonics to FCC Part 97 limits. Use 10 mm spaced air-core coils–10 turns of 1.2 mm enameled wire on a 6 mm mandrel for the first section, 8 turns for the second–followed by 470 pF polystyrene capacitors on each leg. Terminate the filter with a N-type bulkhead connector to minimize radiation losses; PCB traces longer than 15 mm introduce unacceptable insertion loss.

Test the unit with a two-tone 700 Hz/1900 Hz audio signal fed into a DSB exciter set for 10 W PEP output. At 70 W average, intermodulation products (IMD) should measure better than −35 dB relative to either tone. If IMD exceeds −30 dB, reduce input drive by 1 dB and recalibrate the bias potentiometer–overdrive pushes the transistors into class-C operation, generating harmful spurious emissions. Log every adjustment: drain current at idle, full PEP, and THD at 0.5 W intervals to ensure repeatability during contest conditions.

High-Power RF Booster Stage Design: 70W Output at Shortwave Frequencies

Begin with a complementary push-pull stage using MRF323 or RD100HF transistors–both handle 70W continuous dissipation at 35V collector voltage. Bias the devices at 50-100mA quiescent current to maintain efficiency above 55% while minimizing crossover distortion below -40dBc. Use a thermally coupled bias diode mounted on the heatsink; its voltage drop should track the transistors’ Vbe temperature coefficient (~2.2mV/°C) to prevent thermal runaway.

Input matching demands a low-Q transformer with 2:1 impedance ratio, wound on a FT37-43 core. Primary winding requires 8 turns bifilar, secondary 4 turns of 0.5mm enameled wire. Terminate the secondary with a 22Ω resistor in parallel with a 470pF silver mica capacitor to suppress spurious oscillations above 10MHz–critical for stability.

Output network employs a π-section filter: 1.2μH air-core inductor (10 turns 1.2mm wire on 8mm mandrel) shunted by 220pF NP0 capacitors at both ends. This topology delivers VSWR across the target band while attenuating harmonics by >30dB. Ground the chassis at single point near the output connector to eliminate common-mode currents; use 1μF ceramic bypass capacitors at each DC feed point.

Power supply filtering is non-negotiable: 4700μF electrolytic capacitors with 100nF film bypass per rail prevent ripple-induced modulation. Regulate bias voltage to ±12V via LM7812/LM7912–their thermal mass stabilizes bias during transient loads. Include 10A Schottky diodes (e.g., SB560) at each rail to clamp inductive kickback from the output filter.

Cooling demands a forced-air heatsink with 0.5°C/W thermal resistance. Mount transistors using Arctic MX-6 thermal compound and torque screws to 1Nm–uneven pressure creates hotspots. Install a bimetallic thermostat set to 70°C; its NC contacts should interrupt the bias rail if overheating occurs. Never rely on passive convection alone for this power level.

Stability verification requires a vector network analyzer (5kHz–50MHz sweep): target |S21| and phase margin >45° at all frequencies. If peaking occurs, reduce feedback capacitance or increase output network Q. Test with 50Ω dummy load–reflected power above 5W at any drive level indicates parasitic oscillations; revisit layout immediately.

Final RF wiring must use short, direct paths–avoid loops larger than 5mm. Signal grounds should converge at the PCB’s ground plane star point; power grounds separate until this single convergence. Twist DC leads (2 twists/cm) to cancel magnetic coupling. Validate harmonic suppression with a spectrum analyzer: second harmonic must stay below -50dBc, third under -60dBc, or FCC compliance is impossible.

Key Components Selection for a 70W RF Power Stage

Start with the output transistors: IRF510 MOSFETs handle 100V drain-source breakdown but require heatsinks for continuous 70W dissipation. For bipolar alternatives, 2SC2078 (1.5A, 50V) or MRF455 (70W, 36V) pair better in push-pull configurations but demand precise bias adjustments. Thermal resistance must stay below 2°C/W–use TO-220 packages mounted on a finned sink with thermal compound.

• Driver stage: 2N3866 (400mW, 200MHz) provides sufficient gain without distortion. Keep collector resistors under 1kΩ to prevent HF roll-off.
• Bias network: 1N4148 diodes in series establish 0.6V-0.7V per device; replace with TL431 for 2.5V stable reference if temperature drift exceeds 5mV/°C.
• Input/output capacitors: 100nF ceramic (X7R) for bypassing, 10μF electrolytic (low ESR) for coupling. Avoid polyester–self-resonant frequency drops below 5MHz.

Inductors require cores with μ_i=50-100: T37-6 toroids handle 10A without saturation. Wind 12 turns of 18AWG enameled wire for 3μH chokes; verify with an LCR meter at 4MHz to account for skin effect losses. Air-wound coils introduce variability–prefer powdered iron.

Baluns should use trifilar windings on FT50-43 cores (3x 15 turns). Impedance transformation ratios above 4:1 risk common-mode currents–measure with a VNA; return loss must stay below -20dB. For PCB traces, maintain 50Ω microstrip width of 1.5mm on 1.6mm FR4 substrate.

1. Feedback loop: 1kΩ resistor from output to driver base stabilizes gain; add a 10pF capacitor to roll off phase shifts above 10MHz.
2. Power supply: 24V with 2A capability per transistor. Decouple with 10μF tantalum and 1μF ceramic at each stage.
3. Protection: 10A PTC resettable fuse in series with the drain/collector. Reverse voltage diodes (1N5822) across transistor terminals prevent avalanche breakdown.

Step-by-Step Transistor Biasing Circuit Setup

Begin by selecting a 2N3904 NPN transistor or equivalent with a collector-emitter breakdown voltage exceeding 40V and a current gain (hFE) in the 100–300 range. Calculate the base resistor (R_b) using the formula: R_b = (V_cc – V_be) / I_b, where V_cc is the supply voltage (12–24V), V_be is 0.7V for silicon transistors, and I_b is the target base current (typically 10–100µA). For a 12V supply and 50µA base current, R_b = (12 – 0.7) / 0.00005 = 226kΩ; round to the nearest standard value (220kΩ). Use a 1% tolerance resistor for precision.

Voltage Divider Biasing Adjustments

For stable operation, implement a voltage divider network with R₁ and R₂. Set R₂ to 10–50kΩ and calculate R₁ using: R₁ = (V_cc × R₂ / V_b) – R₂, where V_b is the desired base voltage (typically 1–2V). For V_cc = 15V, R₂ = 22kΩ, and V_b = 1.5V, R₁ = (15 × 22k / 1.5) – 22k = 200kΩ. Add a 1µF bypass capacitor across R₂ to minimize AC impedance at the base node. Measure the emitter voltage (V_e) with a multimeter; it should stabilize at V_b – 0.7V.

Finalize the setup by adding an emitter resistor (R_e) of 1–10kΩ to improve thermal stability. The collector resistor (R_c) should align with the load requirements: for a 10mA collector current, R_c = (V_cc – V_ce) / I_c. With V_cc = 15V and target V_ce = 5V, R_c = (15 – 5) / 0.01 = 1kΩ. Verify quiescent current with a series ammeter; adjust R_e incrementally (±1kΩ) if the reading deviates by >5% from the target. Document all values in a schematic for replication.

Input and Output Impedance Matching Techniques for RF Power Stages

Begin impedance matching by selecting a pi-network for frequencies between 1.8 MHz and 14 MHz, ensuring component values adapt to the transistor’s dynamic input characteristics. Use a 50-ohm resistive load as a reference, then calculate shunt capacitance (C1) and series inductance (L) based on the expected Q-factor (target 10–15 for broadband stability). Measure input impedance with a vector network analyzer; adjust C1 until the Smith chart plot centers near the 50-ohm point. Avoid exceeding a Q-factor of 20 to prevent excessive circulating currents in the matching components.

For output matching, employ a low-pass L-network when driving low-impedance loads (e.g., 8–16 ohms). Place a series inductor (L1) followed by a shunt capacitor (C2), calculating values via Z = √(R1 × R2) and X = √(R1 × R2 – R1²), where R1 is the transistor’s output impedance (typically 2–5 ohms for bipolar devices) and R2 is the load resistance. Verify harmonic suppression by checking third-order products at 2–3 dB below the fundamental. Replace standard capacitors with NP0/C0G dielectric types to minimize temperature-induced detuning.

Use transformer-based matching for wideband applications, winding a ferrite toroid (e.g., FT50-43) with a 4:1 ratio for impedance transformation. Ensure primary and secondary windings maintain a 1:1 turns ratio for isolation, while the inductance is tuned to resonant frequency via parallel capacitance. Test intermodulation distortion (IMD) with a two-tone signal (spacing 1 kHz) at 60% of peak power; target IMD levels below -30 dBc. Avoid core saturation by limiting flux density to

Dynamic impedance correction requires a directional coupler at the output, feeding a control loop with a Schottky diode detector. Adjust bias current in real time via a microcontroller sampling the detector output at 10 kHz intervals. Implement a lookup table mapping power levels to optimal bias settings, stored in EEPROM, to compensate for thermal drift. Use a thermistor mounted on the heatsink for coarse correction, scaling bias current linearly between 20°C and 80°C. Ensure the coupler’s directivity exceeds 30 dB to prevent feedback errors.

For high-power stages (>50 W), split the matching network into two sections: a coarse adjustment near the transistor (using high-current air-core inductors) and a fine-tuning section closer to the load (using variable capacitors). Air-core inductors reduce core losses but require spacing of ≥3 mm between turns to prevent arcing at 400 V RMS. Verify tuning by sweeping frequency with a signal generator while monitoring reflected power; reflected power should not exceed 5% of forward power. Document all component values and tuning adjustments per frequency to replicate performance.

Post-tuning validation involves a spectrum analyzer to confirm spurious emissions comply with FCC Part 97 (≤-43 dBc for 30 MHz and below). Replace electrolytic capacitors in bias networks with tantalum or polymer types to improve lifetime under pulse-loading conditions. Record final impedance values and phase angles at 1.8, 3.6, 7.0, 10.1, and 14.2 MHz for future reference, noting variations exceeding ±10% may indicate thermal or mechanical instability.