Basic SMPS Circuit Guide with Easy-to-Follow Schematic

Begin with a flyback converter layout for low-power applications under 100W, as it requires minimal components and provides isolated output. Use a primary-side MOSFET rated for at least twice the input voltage–for a 12V input, select a 60V device to handle transients. Pair it with a Schottky diode on the secondary side, ensuring the reverse voltage rating exceeds the reflected voltage by 20%. Opt for a 1:100 ferrite core transformer ratio if targeting a 5V output to balance efficiency and saturation risks.

For feedback stability, incorporate a TL431 shunt regulator or a dedicated PWM controller like the UC3843. Place a 10kΩ resistor between the optocoupler’s collector and the VCC pin to limit current, and a 1µF capacitor across the compensation pin to dampen oscillations. Avoid ceramic capacitors on the output for high-current loads–electrolytic types with >1A ripple rating perform better under thermal stress. Add a snubber network (22Ω resistor + 1nF capacitor) across the transformer’s primary to suppress voltage spikes.

When prototyping, prioritize ground planes–separate analog and switching grounds, connecting them at a single star point near the input filter capacitor. Use 100µF/25V bulk capacitance on the input for 12V sources, with a 10Ω resistor in series to soft-start the inrush current. For 240VAC applications, replace the MOSFET with an IGBT and increase the snubber’s resistor to 47Ω to handle switching losses. Validate the design with a thermal camera–hotspots above 85°C indicate incorrect component sizing or layout flaws.

For EMI compliance, add a common-mode choke after the bridge rectifier and a 10nF Y-rated capacitor between primary and secondary grounds. Test with a spectrum analyzer: peaks above -60dBµV at 150kHz suggest inadequate filtering. Use 2.2µH inductors in series with input/output lines for differential-mode noise suppression. If space allows, replace the bridge rectifier with individual diodes for lower forward voltage drop in high-efficiency builds.

Designing a Basic Power Supply Schematic for Makers

Start with a flyback converter for low-to-medium power applications under 150W–it eliminates the need for an output inductor, reducing component count. Use an integrated controller like the TOP258PN or ViPer22A for built-in switching, feedback, and protection. These ICs simplify layout by combining MOSFET, oscillator, and error amplifier in a single package, cutting design time by 40%.

Place input capacitors (10μF–100μF X-rated film or 47μF–220μF electrolytic) directly across the bridge rectifier output to suppress high-frequency noise. For 230VAC inputs, select capacitors rated for 400VDC; 120VAC inputs require 200VDC. Keep trace lengths under 20mm between capacitors and the controller to prevent voltage spikes above 20% of the nominal input.

Critical Component Placement

Place the snubber network (470Ω resistor + 220pF ceramic capacitor) across the primary winding of the transformer to clamp voltage transients exceeding 100V/μs. Position it within 5mm of the winding terminals–longer distances increase leakage inductance, reducing efficiency by 3–5%. For secondary-side regulation, use a TL431 shunt regulator paired with a PC817 optocoupler to isolate feedback.

Choose a high-frequency transformer core such as EE20 or EFD20 for frequencies between 65kHz–130kHz. Wind the primary first, followed by a 30–50 turns auxiliary winding (for bias supply), then the secondary. Keep windings tight and layer insulation (polyimide tape) between them to reduce capacitance and EMI. Test the winding ratio with a 10Ω load–voltages should stabilize within 5% of target (e.g., 5V ±0.25V).

Add a 10μH–33μH ferrite bead on the output line to filter high-frequency noise above 1MHz. For protection, include a 1A PTC resettable fuse on the input and a TVS diode (e.g., P6KE200A) rated at 120% of the maximum input voltage. Avoid placing the TVS near sensitive components–its clamp energy can radiate and disrupt nearby traces.

Verify performance with an oscilloscope: probe the MOSFET drain node–ringing should not exceed 1.2× the input voltage. Measure efficiency at 20%, 50%, and 100% load; expect 75–85% for non-synchronous designs. If efficiency drops below 70%, check transformer saturation (reduce primary turns) or snubber values (increase resistance). Document trace widths–1mm (1oz copper) handles 1A; 2mm handles 2.5A without overheating.

Core Elements for Building Your Own Power Converter

Select a high-frequency transformer with a ferrite core, such as TDK PC40 or EPCOS N87 material, to ensure minimal hysteresis losses at switching frequencies above 50 kHz. Wind primary and secondary coils with at least 200 strands of 0.1mm magnet wire for reduced skin effect, and maintain interleaving between windings to cut leakage inductance below 10 μH. Verify core saturation margins by calculating B_max = V_in × D / (f × N × A_e); keep B_max under 0.3 T for reliability.

MOSFETs rated for 600V and R_DS(on) under 0.3Ω–examples include Infineon IPA60R380P6 or STW45NM60–reduce conduction losses. Pair each switch with a UF4007 ultrafast diode for gate protection, and use a bootstrap circuit (1N4148 diode + 1 μF capacitor) to drive high-side configurations. Thermal calculations: ensure junction temperature stays below 125°C with heatsinks rated for 5°C/W or better, factoring in switching losses P_sw = 0.5 × V_ds × I_d × f × (t_rise + t_fall).

Opt for a TL494 or UC3843 PWM controller IC with built-in error amplifiers and soft-start capacitors (100 nF X7R) to prevent inrush currents. Feedback isolation requires a HCPL-3120 optocoupler or similar, with a 2 mA LED current set via a 1.5kΩ resistor, ensuring common-mode noise immunity up to 10 kV/μs. Input filtering: place a 10 μH common-mode choke before a 220 μF/450V electrolytic capacitor to suppress EMI below EN55022 Class B limits.

Critical Passives and Safety Measures

Output capacitors must handle ripple currents above 3 A_rms–use low-ESR variants like Nichicon LGU or Panasonic FR series, sized at C = I_out × D / (f × ΔV_out), where ΔV_out < 50 mV_pp. Snubber networks (270 Ω resistor + 2.2 nF ceramic capacitor) across MOSFET drains clamp voltage spikes below 550V. Fuse selection: time-lag 5×20mm types rated 2× I_in(max), tested to open within 5 ms at 10× overload. Ground planes on PCB copper pours thicker than 2 oz reduce EMI by 20 dB; isolate primary and secondary returns with a 8mm creepage distance.

Step-by-Step Wiring of a Flyback Power Converter

Select a switching transistor rated for at least 1.5 times the input voltage and 2 times the expected peak current. For most 12V to 48V outputs, a 600V MOSFET like the IRF840 ensures margin against voltage spikes during turn-off. Verify the gate threshold voltage aligns with your driver IC–typically 3V to 10V–for reliable switching.

Wind the primary coil with 22 AWG magnet wire, calculating turns using the formula: N_p = (V_in_min × t_on) / (B_max × A_e). For a ferrite core with A_e = 1.2 cm² and B_max = 0.3T, a 12V input at 100 kHz with 50% duty cycle requires ~30 turns. Space windings evenly to reduce leakage inductance below 3% of primary inductance.

Connect the feedback winding in *phase opposition* to the primary, ensuring the dot convention marks the start. A 5-turn secondary on the same bobbin, using 24 AWG wire, provides galvanic isolation. Snub the coil with an RC network: R = 100Ω (1W) and C = 1nF (X7R dielectric), placed across the primary to clamp overshoot under 1.2× V_in.

Attach a Schottky diode to the secondary, rated for 1.5× the output voltage and 2× the load current. For a 5V/2A output, use an MBR1045 (45V, 10A) to minimize forward drop and reverse recovery losses. Add a 10µF ceramic capacitor (X5R) directly across the output terminals to filter high-frequency ripple below 50mV_p-p.

Implement current-mode control with a UC3843 driver IC. Connect the sense resistor (R_sense = 0.25Ω, 1W) in series with the MOSFET source. Set the oscillator frequency via R_t = 10kΩ and C_t = 1nF, yielding ~100 kHz. Tie the compensation network (22kΩ + 1nF) to the error amplifier to achieve

Verify insulation between primary and secondary with a 500V megohmmeter; resistance should exceed 10MΩ. Test under load with a current-limited supply, monitoring for subharmonic oscillation–indicated by irregular switching waveforms. Adjust R_t or C_t if the duty cycle exceeds 45% at low line conditions.

Enclose the assembly in a grounded metal case, spacing high-voltage traces ≥4mm from low-voltage paths. Use a Y1-rated capacitor (470pF) for EMI filtering between primary and secondary grounds. Final efficiency should exceed 85% at full load, with conducted emissions under CISPR 22 Class B limits.

Common Input Voltage and Output Adjustments

For most low-power switching regulators, design for an input range of 8-36V DC to cover applications from battery packs (2S-8S Li-ion) to industrial supplies. Below 9V, increase the input capacitance to 470µF (low ESR tantalum) to prevent voltage sag during transient loads. Above 30V, derate the MOSFET’s V_DS by 30% (e.g., 40V-rated part for 36V input) and add a 18V Zener diode across the gate driver to clamp overshoot. For universal AC adapters (85-265VAC), front-end with a 27µF/400V electrolytic and a 1N4007 bridge; buck stage inductance scales inversely–47µH at 12V, 33µH at 24V, 22µH at 36V–measured at 1kHz, 1A ripple.

Output Voltage (V)	Feedback Ratio (R1:R2)	Inductance (µH)	Peak Current (A)
3.3	1kΩ : 2.2kΩ	68	1.8
5	1kΩ : 3.9kΩ	47	2.5
12	10kΩ : 33kΩ	22	4.2
24	10kΩ : 51kΩ	10	6.0

Compensate feedback loop with a 4.7nF phase-lead capacitor across R1 for stable crossover below 100kHz; above 50W, replace the diode with a synchronous MOSFET (V_GS ≤12V) and halve the gate resistor to 4.7Ω to cut switching losses. Adjust output voltage trimming by swapping R2 with a 50kΩ multi-turn potentiometer and monitor load regulation at ±0.5% across the full input range.