UC3845 Switching Power Supply Controller Circuit Design and Analysis

Start with a 12V to 24V input range when designing a flyback or forward converter using this PWM controller. Keep the sense resistor (R_s) under 1Ω–values of 0.2Ω to 0.5Ω ensure stable current limiting without excessive power dissipation. Calculate the maximum duty cycle using D_max = (V_out + V_f) / V_in(min), where V_f is the diode forward voltage. For 5V output, a 90% duty cycle at 12V input is typical.

Place the compensation network (R_c, C_c) directly between the error amplifier output (pin 1) and the negative input (pin 2). Use R_c = 10kΩ–50kΩ and C_c = 1nF–10nF for a 50kHz to 200kHz switching frequency. Higher frequencies need smaller C_c to avoid phase margin loss. Add a 100pF to 1nF capacitor from pin 2 to ground to filter high-frequency noise.

For stable operation, connect a 10kΩ to 100kΩ resistor from the reference output (pin 8) to the error amplifier input (pin 2). This sets the initial startup voltage and prevents erratic behavior during transient loads. Use a soft-start capacitor (C_ss) of 10nF to 1µF at pin 8–larger values slow inrush current but extend startup time.

Size the gate resistor (R_g) for the MOSFET at 10Ω to 100Ω to balance switching speed and ringing. High-power applications (>50W) benefit from a 2Ω–10Ω resistor in series with the gate to reduce EMI. Keep the high-voltage trace from the MOSFET drain to the transformer primary short and wide to minimize inductance.

Add a 1N4148 diode across the sense resistor to protect against negative voltage spikes during commutation. For snubber design, use R_snub = 10Ω–100Ω and C_snub = 100pF–1nF across the primary winding. Adjust values based on ringing frequency: R_snub × C_snub ≈ 1 / (2π × f_ring).

Practical Implementation of the PWM Controller Layout

Begin with a low-ESR timing capacitor (typically 1nF to 100nF) between pin 4 (RT/CT) and ground. Ensure the capacitor’s dielectric is X7R or better to minimize temperature drift–film types introduce phase errors that degrade stability. Pair it with a precision resistor (1% tolerance, metal film) from RT/CT to VREF (pin 8) to set the switching frequency. For 100kHz operation, use 10kΩ and 1nF; for 500kHz, drop to 2kΩ and 220pF. Measure the actual frequency under load–production spreads on internal comparators can shift it ±20%.

Isolate the feedback path by routing the optocoupler collector (commonly PC817) directly to the COMP pin (pin 1). Bypass this node with a 1µF ceramic cap to ground to suppress high-frequency noise–even 20mV spikes at 1MHz can falsely trigger the PWM latch. Keep the COMP trace shorter than 15mm; longer traces act as antennas picking up radiated EMI from the power stage. If isolation exceeds 3kV, add a 100Ω series resistor at the COMP input to dampen oscillations caused by parasitic capacitance.

Connect the current-sense resistor (Rs) between pin 3 (ISENSE) and the source of the power MOSFET. Use a non-inductive shunt (e.g., Vishay WSR series) rated at least 2x the peak current to prevent thermal drift. Scale Rs for 1V threshold: for 5A peak, 0.2Ω gives 1V drop. Ground the sense node through a star point tied only to the controller’s analog ground–never share this path with switching currents. Solder the resistor directly to the MOSFET pad to avoid lead inductance, which distorts the ramp waveform and causes premature shutdowns.

Decouple VCC (pin 7) and VREF (pin 8) with separate 0.1µF ceramics placed within 2mm of the package. VCC tolerates 10V–30V, but derate to 16V for reliable startup; internal UVLO hysteresis is 6V, so transient dips below 12V may reset the controller. Add a 10µF bulk cap on VCC if the supply impedance exceeds 0.5Ω at 100kHz–this prevents false UVLO trips during MOSFET turn-off. Avoid electrolytics on VREF–their ESR skews the internal 5V bandgap reference, leading to erratic duty cycles.

Gate drive (pin 6) requires a 10Ω–22Ω series resistor to the MOSFET gate to limit di/dt. Higher values increase switching losses but reduce EMI; lower values risk gate-ringing from trace inductance. Use a Schottky diode (1N4148) across the gate resistor to clamp negative transients when the MOSFET turns off rapidly. The gate drive can source/sink ±1A, but exceeding 12V on the gate causes internal clamp failure–use a Zener (BZX84C12) if the drive exceeds 14V. Keep the gate trace impedance below 5Ω to prevent false triggering from ground bounce.

Thermal layout centers on the exposed pad (if present) or the ground pins (4, 5). Solder these directly to a 1-inch² copper pour on the PCB’s bottom layer, connected to the main ground plane via multiple vias. The controller’s junction temperature rises 12°C/W without heatsinking; at 1.2W dissipation, it reaches 85°C ambients. For higher power, add a thermal pad under the package or use a TO-220 variant with a heatsink. Never route high-current traces under the controller–inductive coupling into the VCC or COMP nodes corrupts regulation.

Pin Configuration and Functionality of the PWM Controller in SMPS Layouts

Begin by mapping the Compensation (Pin 1) to stabilize the feedback loop with a 0.1µF ceramic capacitor to ground and a series resistor (1–10kΩ) to the error amplifier output. This prevents high-frequency noise from disrupting regulation while maintaining fast transient response.

The Voltage Feedback (Pin 2) requires a precision voltage divider from the output. Use 1% tolerance resistors (10kΩ and 2.2kΩ for a 5V output) to ensure ≤1% error in regulation. Bypass with a 1nF capacitor to filter switching noise, reducing ripple by 30–40% without compromising loop bandwidth.

Critical Power and Ground Connections

VCC (Pin 7) must be decoupled with a 1µF X7R capacitor placed ≤2mm from the pin to prevent latch-up during startup. Add a 1N4148 diode from the bias winding to Pin 7 to clamp the voltage below 34V, protecting the controller from overvoltage spikes. A 10µH inductor in series with the input supply filters conducted EMI, meeting CISPR 22 Class B limits.

Gate Drive (Pin 6) outputs a 1A peak current; route traces with ≤0.5Ω impedance and a minimum width of 0.5mm to prevent voltage drop. Use a 10Ω series resistor to dampen ringing, reducing MOSFET turn-off overshoot by 50%. For high-side drive applications, isolate the return path to avoid ground bounce above 200mV, which can trigger false shutdowns.

• Current Sense (Pin 3): Place a 100Ω resistor in series with the sense resistor (0.1–0.5Ω) to limit input current. Add a 1nF capacitor across Pin 3 and the power ground to filter switching noise, improving noise immunity by 25dB. Avoid ground loops by star-connecting the sense resistor to the controller’s ground.
• Oscillator (Pin 4): Set switching frequency with a 10kΩ resistor to ground and a 1nF timing capacitor. For 250kHz operation, use 1% tolerance components to achieve ±5% frequency stability. Synchronize multiple controllers by injecting a 1V–5V square wave into this pin.
• Shutdown (Pin 5): Connect to a fault detection circuit (e.g., over-temperature or UVLO) via an open-collector transistor. A 10kΩ pull-up resistor to VREF ensures clean logic levels, preventing false triggers during power transients.

Reference voltage (VREF, Pin 8) must be loaded with ≤10mA; exceeding this degrades accuracy. Decouple with a 0.1µF capacitor and a 10µF tantalum for low-frequency stability. For isolated designs, derive the feedback network from this pin rather than the output to avoid ground shift errors.

Thermal considerations: Place the controller ≥5mm from heat-generating components (e.g., MOSFETs, diodes) to prevent thermal coupling. Use a 4-layer PCB with 1oz copper for the power planes to dissipate ≥1W without heatsinks. For ambient temperatures above 70°C, derate the maximum duty cycle by 1% per °C to prevent overheating of the internal 500mW regulator.

Step-by-Step Wiring of a Current-Mode PWM Controller for Flyback Topologies

Begin by connecting the feedback winding of the transformer to the error amplifier input pin via a precision resistor divider. Use 10 kΩ for the upper resistor and 2.2 kΩ for the lower resistor to scale the output voltage to 2.5 V, matching the internal reference. Ensure the transformer’s auxiliary winding polarity aligns with the flyback phase–reverse polarity will cause erratic switching and potential damage.

Place a 1 nF ceramic capacitor between the compensation pin and ground to stabilize the error amplifier’s response. For most 50–100 kHz applications, pair it with a 10 kΩ resistor in parallel to form a low-pass filter with a cutoff around 15 kHz. Adjust values if overshoot exceeds 5% during load transients–reduce capacitance for faster response, increase resistance for damping.

Component	Value (Typical)	Purpose
RT (Timing Resistor)	8.2 kΩ–22 kΩ	Sets oscillator frequency (f = 1.72 / RT × CT)
CT (Timing Capacitor)	1 nF–10 nF	Works with RT to define switching frequency
Current Sense Resistor	0.1 Ω–0.5 Ω	Converts primary current to voltage for PWM

Wire the current sense resistor in series with the MOSFET source and ground. Keep lead lengths under 2 mm to minimize parasitic inductance, which distorts the sensed waveform. A 0.22 Ω resistor yields 1 V at 4.5 A peak current–verify with an oscilloscope under full load. If the signal rings excessively, add a 100 pF snubber capacitor across the resistor.

Connect the gate drive output to the MOSFET via a 10 Ω–47 Ω resistor to limit gate current and prevent shoot-through. For higher-power designs (>50 W), use a totem-pole driver IC (e.g., TC4427) to improve rise/fall times. Isolate the gate drive path from high-current loops to avoid false triggering from inductive coupling.

Add a soft-start capacitor (0.1 µF–1 µF) between the soft-start pin and ground to ramp the duty cycle over 5–20 ms. Larger capacitors extend startup time but reduce inrush current. Omit this component only if fast startup is critical–uncontrolled turn-on risks transformer saturation and MOSFET stress.

Implement overcurrent protection by setting the clamp voltage on the current sense pin. A diode (e.g., 1N4148) from the internal 1 V reference to the sense pin limits the maximum duty cycle at 90%. For tighter control, use a zener diode to clamp at 0.8–1.0 V, reducing peak current during faults.

Terminate the layout with a ground plane under the controller to minimize noise coupling. Separate analog ground (feedback, compensation, reference) from power ground (current sense, gate drive). Route traces for RT and CT away from switching nodes to avoid frequency drift. Test stability by injecting a 1 A–2 A load step–ringing should settle within three cycles.